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Circuit architecture for use in system for measuring and compensating signal delay on source synchronous clocked data buses, has multiplexer for selecting core clock or sampling clock for clocking clockable receiving unit of data line
Circuit architecture for use in system for measuring and compensating signal delay on source synchronous clocked data buses, has multiplexer for selecting core clock or sampling clock for clocking clockable receiving unit of data line
The circuit architecture has multiple data lines (4), where each data line has a clockable transmitting unit (15) and receiving unit (6). A core clock line (5) is provided for allocating of a core clock (RX-clk) to the clockable transmitting and receiving units. A sampling line (9) is provided for allocating a sampling clock (s-clk) for asynchronous subsampling. A multiplexer (7) is provided for selecting the core clock or the sampling clock for clocking the clockable receiving unit of the data line. The multiplexer is connected with another receiving unit of sampling the core clock. Independent claims are included for the following: (1) a method for determining and compensating of a signal delay of a data line relative to another line of a circuit architecture; and (2) a system with signal processing unit.
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