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首页> 外国专利> digital / analog converter that generates waveforms decreasing exponential type for the feedback loop of a sigma-delta converter continuous time.

digital / analog converter that generates waveforms decreasing exponential type for the feedback loop of a sigma-delta converter continuous time.

机译：数模转换器，可为sigma-delta转换器连续时间的反馈环路生成呈指数级下降的波形。

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Digital / Analog converter which generates waveforms for decreasing exponential type feedback loop converter Sigma- Delta continuous time.; The Digital converter / Analog circuit proposed generates waveforms decreasing exponential type for the feedback loop of a sigma-delta converter continuous time. It allows to significantly reduce clock jitter sensitivity of the Sigma-Delta converter continuous time.; Consists of a capacitor (3), two resistors (6) and six switches (2), (4) and (5) which are controlled by the corresponding logic circuit (Figure 5). Actually, we have used two capacitors (3) with their folded to consider the parasitic capacitances associated with the lower plate of the capacitor with the substrate terminal.; The proposed circuit achieves a significant reduction in this sensitivity to jitter by generating waveforms return type zero delayed half cycle (HRZ) and decreasing exponential growth in the feedback loop of the converter Sigma-Delta continuous time.
机译：数模转换器产生波形，以减小指数型反馈环路转换器 Sigma- Delta连续时间。提出的数字转换器/模拟电路会为sigma-delta转换器连续时间的反馈回路生成递减指数型的波形。它可以显着降低Sigma-Delta转换器连续时间的时钟抖动灵敏度。由一个电容器（3），两个电阻器（6）和六个开关（2），（4）和（5）组成，它们由相应的逻辑电路控制（图5）。实际上，我们使用了两个折叠的电容器（3）来考虑与带有基板端子的电容器下板相关的寄生电容。所提出的电路通过生成波形返回类型零延迟半周期（HRZ）并减少转换器Sigma-Delta连续时间的反馈环路中的指数增长，从而显着降低了对抖动的敏感性。

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