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LOGIC CIRCUIT, CLOCK SKEW REDUCTION SYSTEM AND CLOCK SKEW REDUCTION METHOD
LOGIC CIRCUIT, CLOCK SKEW REDUCTION SYSTEM AND CLOCK SKEW REDUCTION METHOD
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机译：逻辑电路，时钟偏移减少系统和时钟偏移减少方法
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摘要
PROBLEM TO BE SOLVED: To provide a logic circuit, a clock skew reduction system and a clock skew reduction method, allowing reduction of a clock skew between respective F/Fs, and allowing reduction of an area of a semiconductor chip to reduce power consumption of a semiconductor integrated circuit.;SOLUTION: This logic circuit has: a final-stage buffer cell 100 amplifying an inputted clock; and the flip-flops F/F1a-h adjacent to the buffer cell, and inputted with the clock from the buffer cell.;COPYRIGHT: (C)2006,JPO&NCIPI
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