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Integrated semiconducting memory has read amplifier(s), pair(s) of bit lines with n segment bit line pairs for separate electrical connection to read amplifier; n is natural number greater than 1
Integrated semiconducting memory has read amplifier(s), pair(s) of bit lines with n segment bit line pairs for separate electrical connection to read amplifier; n is natural number greater than 1
The integrated semiconducting memory has at least one read amplifier (SA) and at least one pair of bit lines (BL) consisting of n segment bit line pairs (SBL) that can be electrically connected to the read amplifier separately from each other, where n is a natural number greater than 1. Each segment bit line pair can be electrically connected to the read amplifier by a switching arrangement (SW1-SW3).
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