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Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods
Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods
A carrier substrate, or interposer, for use in a chip-scale package. The interposer is formed from a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar to that of the semiconductor device to be secured thereto. A chip-scale package including the interposer is formed by aligning a substrate including a plurality of interposers over semiconductor devices carried upon a wafer or other large-scale substrate. Bond pads of the semiconductor devices are exposed through insulator-lined apertures of the interposers. The apertures are filled with electrically conductive material and conductive structures are secured to the apertures so as to communicate with corresponding bond pads. The resulting chip-scale packages may then be severed or diced from the substrate and wafer. Apparatus and methods for simultaneously testing multiple, physically connected chip-scale packages are also disclosed.
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