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UNIT BINARY COUNTER, SYNCHRONOUS BINARY COUNTER AND FREQUENCY DIVIDER TO WHICH THE UNIT BINARY COUNTER IS APPLIED
UNIT BINARY COUNTER, SYNCHRONOUS BINARY COUNTER AND FREQUENCY DIVIDER TO WHICH THE UNIT BINARY COUNTER IS APPLIED
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机译：适用于单位二进制计数器的单位二进制计数器，同步二进制计数器和频率除法
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摘要
The invention relates to a binary counter stable. / p & & p & a meter according to the invention comprises a counter plurality elementary mounted in cascade. Each counter elementary is formed by a half - adder having two entrees b, c, a "sum" output s and a "carry" output r. the "sum" output s is connected at the input of a master flip-flop - slave m e, whose output q is looped on an input of the half - adder a. the flip-flops master and slave e are ordered by the two complementary shapes (h and h) of a single clock signal. The "carry" output r of a half - adder is connected on the input b of the half - adder has follows. / p & & p & application to the synchronous counters and the frequency dividers, more particularly in the microwave frequencies and in the form of a circuit integrated.
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