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Architecture design and process for manufacturing monolithic integrated 3D CMOS logic and memory
Architecture design and process for manufacturing monolithic integrated 3D CMOS logic and memory
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机译：制造单片集成3D CMOS逻辑和内存的建筑设计与过程
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摘要
A semiconductor device is provided. The device includes a plurality of pairs of transistors stacked over a substrate. Each of the plurality of transistor pairs includes an n-type transistor and a p-type transistor stacked on each other. The device further includes a plurality of gate electrodes stacked on the substrate in a stepwise configuration. The plurality of gate electrodes are electrically connected to the gate structure of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects stacked on the substrate in a stepwise configuration. The plurality of S/D local interconnects are electrically connected to the source region and the drain region of the plurality of transistor pairs.
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