A 48 mW 18 Gb/s Delay-Line Based 1:4 Demultiplexer in 45-nm RFSOI CMOS

机译：一个基于45纳米RFSOI CMOS的基于48 mW 18 Gb / s延迟线的1：4解复用器

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This paper presents the design and characterization of a new delay-line based demultiplexer (Demux). The Demux works by setting the delay of each delay-element in the delay-line equal to the period of the input symbol and the delay of the delay-line equal to the period of the sampling clock. Once the delay-line is sampled, each sampled output represents a unique symbol in the input symbol sequence. As opposed to the traditional tree-architecture Demux, the proposed delay-line Demux dissipates power only in the delay-line. In addition to design simplicity, the delay-line Demux also offers power and area advantages over tree Demux when scaled to a higher channel count. Designed in 45-nm RFSOI CMOS, the Demux achieves 2.6 pJ/symbol of energy figure, which, to the best of the authors knowledge, is the best reported among inductor-less CMOS Demuxes.

机译：本文介绍了一种新的基于延迟线的解复用器（Demux）的设计和特性。多路分配器通过将延迟线上的每个延迟元素的延迟设置为等于输入符号的周期，并将延迟线的延迟设置为采样时钟的周期来工作。一旦对延迟线进行了采样，每个采样的输出就会在输入符号序列中代表一个唯一的符号。与传统的树结构Demux相比，建议的延迟线Demux仅在延迟线上消耗功率。除了简化设计之外，延迟线Demux在缩放到更高的通道数时，还比树型Demux具有功耗和面积优势。 Demux采用45纳米RFSOI CMOS设计，可实现2.6 pJ /符号的能量系数，据作者所知，这是无电感器CMOS Demux中报道最多的。

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《2019 15th Conference on Ph.D Research in Microelectronics and Electronics》|2019年|213-216|共4页
会议地点 Lausanne(CH)
作者
Sami Ur Rehman; Mohammad Mahdi Khafaji; Corrado Carta; Frank Ellinger;
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作者单位

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden 01069, Germany;

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden 01069, Germany;

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden 01069, Germany;

Chair of Circuit Design and Network Theory, Technische Universität Dresden, Dresden 01069, Germany;

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原文格式 PDF
正文语种 eng
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关键词
Delays; Clocks; Inverters; Latches; Tin; Jitter; Multiplexing;

机译：延迟;时钟;逆变器;锁存器;锡;抖动;多路复用;;

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专利

1. A 25-Gb/s 270-mW Time-to-Digital Converter-Based$8{imes}$Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS [J] . Sami Ur Rehman, Mohammad Mahdi Khafaji, Corrado Carta, IEEE transactions on circuits and systems . I , Regular papers . 2018,第11期

机译：基于25 Gb / s 270 mW时间数字转换器的 $ 8 { times} $ 在45nm SOI CMOS中过采样输入延迟的数据接收器
2. A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS [J] . Rehman Sami Ur, Khafaji Mohammad Mahdi, Ferschischi Ali, IEEE transactions on circuits and systems. II, Express briefs . 2020,第5期

机译：用于25 GB / S数据接收器的0.2-1.3 ns范围延迟控制方案使用45-nm CMOS中的基于副本延迟线的延迟锁定循环循环循环
3. A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS [J] . Sajjad Moazeni, Sen Lin, Mark Wade, Solid-State Circuits, IEEE Journal of . 2017,第12期

机译：基于45nm SOI CMOS的环形谐振器光学DAC的40Gb / s PAM-4发送器
4. A 48 mW 18 Gb/s Delay-Line Based 1:4 Demultiplexer in 45-nm RFSOI CMOS [C] . Sami Ur Rehman, Mohammad Mahdi Khafaji, Corrado Carta, Conference on Ph.D Research in Microelectronics and Electronics . 2019

机译：基于48 MW 18 GB / S延迟线的1：4在45-NM RFSOI CMO中的多路分解器
5. A 1-16 Gb/s all-digital phase-interpolator based clock and data recovery circuit and study on reliability of deep submicron CMOS transistors at cryogenic temperature [D] . Wu, Guoying. 2014

机译：基于1-16 GB / S的全数字阶段内插器的时钟和数据恢复电路及深亚微米CMOS晶体管在低温温度下的可靠性研究
6. A Sub-mW 18-MHz MEMS Oscillator Based on a 98-dBΩ Adjustable Bandwidth Transimpedance Amplifier and a Lamé-Mode Resonator [O] . Anoir Bouchami, Mohannad Y. Elsayed, Frederic Nabki 2019

机译：基于98dBΩ可调带宽跨阻放大器和Lamé模式谐振器的SubmW 18MHz MEMS振荡器
7. 6.8MW 2.5GB/S AND 42.5MW 5GB/S 1:8 CMOS DEMULTIPLEXERS [O] . Shanfeng Cheng, Jose Silva-martinez 2015

机译：6.8mW 2.5GB / s和42.5mW 5GB / s 1：8 CmOs解复用器

A 48 mW 18 Gb/s Delay-Line Based 1:4 Demultiplexer in 45-nm RFSOI CMOS

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