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首页> 外文会议>18th International Symposium on VLSI Design and Test >A novel architecture for QPSK modulation based on time-mode signal processing
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A novel architecture for QPSK modulation based on time-mode signal processing

机译：基于时间模式信号处理的新型QPSK调制架构

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With shrinking process technology, the scale of integration has increased significantly for digital design. Therefore, the increase in operating frequency, and attempt to reduce area and power has been addressed to large extent. On the contrary, it has lesser impact on its analog counterpart and has not been able to catch up with the respective design metrics pertaining to digital design. This paper presents a new design method for Quadrature Phase Shift Keying (QPSK) modulation technique using Time Mode Signal Processing (TMSP) technique. This method uses a digital clock signal acting as the carrier signal and thus provides a digital interface at the output. A 2 bit input digital code modulates the delay of the clock and hence carries the information in it. The proposed design yields a low voltage and low power alternative to its known analog counterparts. We implemented the design using 0.18μm TSMC CMOS technology. The power supply is kept at 2V, while the carrier frequency remains 250MHz. The results for both pre and post-layout simulations yield significant improvement in layout area, power dissipation and signal-to-noise ratio (SNR) as compared to a conventional design for QPSK modulation.
机译：随着工艺技术的不断缩小，数字设计的集成规模已大大增加。因此，已经在很大程度上解决了工作频率的增加以及试图减小面积和功率的尝试。相反，它对模拟对象的影响较小，无法赶上与数字设计有关的各个设计指标。本文提出了一种使用时间模式信号处理（TMSP）技术的正交相移键控（QPSK）调制技术的新设计方法。该方法使用数字时钟信号作为载波信号，从而在输出端提供数字接口。 2位输入数字代码可调制时钟延迟，从而在其中携带信息。所提出的设计提供了一种低电压和低功耗的替代方案，可替代其已知的模拟同类产品。我们使用0.18μm的TSMC CMOS技术实施了该设计。电源保持在2V，而载波频率保持250MHz。与传统的QPSK调制设计相比，布局前和布局后仿真的结果均显着改善了布局面积，功耗和信噪比（SNR）。

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