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18th International Symposium on VLSI Design and Test

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1.A spare link based reliable Network-on-Chip design

机译：基于备用链接的可靠片上网络设计
- 作者：Chatterjee Navonil;Prasad N.;Chattapadhya Santanu
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Fault tolerant Routing;
- Network-on-Chip;
- Reliability;
- Spare Link;
2.An analytical delay model for CMOS Inverter-Transmission Gate structure

机译：CMOS反相器-传输门结构的解析延迟模型
- 作者：Romi Mohammad Shueb;Alam Naushad;Yasin M.Yusuf
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Delay model;
- Inverter;
- Process-Voltage-Temperature Variability;
- Transmission Gate;
3.A locally reconfigurable Network-on-Chip architecture and application mapping onto it

机译：本地可重新配置的片上网络架构及其上的应用程序映射
- 作者：Soumya J.;Sharma Ashish;Chattopadhyay Santanu
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Communication cost;
- Integer Linear Programming;
- Reconfiguration;
4.Signature analysis for synthesis of reversible circuit

机译：可逆电路综合的签名分析
- 作者：Das Palash;Mondal Bikromadittya
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Circuit synthesis;
- Quantum cost;
- Reversible circuit;
- Reversible gate;
- Signature-V;
5.FPGA-based real-time object tracker using modified particle filtering and SAD computation

机译：使用改进的粒子滤波和SAD计算的基于FPGA的实时对象跟踪器
- 作者：Singh Sanjay;Saini Ravi;Saurav Sumeet;Saini Anil K;Shekhar Chandra;Vohra Anil
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- FPGA Implementation;
- Object Tracking;
- VLSI Architecture;
- Video Surveillance System;
6.An LUT based RNS FIR filter implementation for reconfigurable applications

机译：基于LUT的RNS FIR滤波器实现可重新配置的应用
- 作者：Kotha Srinivasa Reddy;Bajaj Sumit;Kumar Sahoo Subhendu
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Altera DSP Builder;
- Reconfigurable FIR Filter;
- Residue Number System;
- Shift and Add ap-proach;
7.An efficient hardware architecture for stereo disparity estimation

机译：用于立体视差估计的高效硬件架构
- 作者：Joseph Fradaric;Francis Kiran;Hore Archita;Roy Siddhanta;Josephine S.;Paily Roy P
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
8.Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications

机译：低功耗SoC应用中22nm节点外延三角形掺杂沟道MOS晶体管反向衬底偏置效应的研究
- 作者：Bairagi Debayan;Pandit Soumya
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
9.Pipelined FFT architectures for real-time signal processing and wireless communication applications

机译：适用于实时信号处理和无线通信应用的流水线FFT架构
- 作者：Glittas Antony Xavier;Lakshminarayanan G
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- BPSK;
- Fast Fourier transform (FFT);
- Real-valued FFT;
- Real-valued signals;
- Two-parallel;
10.High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications

机译：高介电常数隔离物对基于无结FinFET的电路/ SRAM应用的影响
- 作者：Nehra Dilsukh;Pal Pankaj Kumar;Kaushik B.K.;Dasgupta S.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- CMOS inverter;
- FinFETs;
- Junctionless transistors (JLT);
- SRAM cell;
- access time;
- high-k spacer;
- ring-oscillator;
- short channel effects (SCEs);
- static noise margin (SNM);
11.A novel architecture for QPSK modulation based on time-mode signal processing

机译：基于时间模式信号处理的新型QPSK调制架构
- 作者：Saha Sumit;Kar Bapi;Sur-Kolay Susmita
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- low power;
- modulation;
- noise immunity;
- quadrature phase shift keying;
- time mode signal processing;
12.Distributed adaptive routing for spidergon NoC

机译：蜘蛛NoC的分布式自适应路由
- 作者：Bishnoi Rimpy;Kumar Pankaj;Laxmi Vijay;Gaur Manoj Singh;Sikka Apoorva
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- NoC SoC;
- Path diversity;
- adaptive;
13.Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers

机译：通过使用SMT求解器扩展基于路径的等效性检查器来扩展翻译验证的范围
- 作者：Banerjee Kunal;Mandal Chittaranjan;Sarkar Dipankar
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Finite State Machine with Datapath (FSMD);
- Normalization;
- SMT Solvers;
- Translation Validation;
14.Operation-aware assist circuit design for improved write performance of FinFET based SRAM

机译：感知操作辅助电路设计，用于改善基于FinFET的SRAM的写入性能
- 作者：Prajapati Ekta;Yadav Nandakishor;Pattanaik Manisha;Sharma G.K.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Assist Circuits;
- Cell supply suppression;
- FinFET;
- Negative Bit-Line Bias;
- Process Variation;
- SRAM;
- Short Channel Effects;
15.Power optimized PLL implementation in 180nm CMOS technology

机译：采用180nm CMOS技术的功耗优化PLL实施
- 作者：Sreehari Patri;Devulapalli Pavankumarsharma;Kewale Dhananjay;Asbe Omkar;Prasad K S R Krishna
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
16.250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifier

机译：250mA超低压降稳压器，具有高转换速率，双循环折叠共源共栅误差放大器
- 作者：Patri Sreehari Rao;Alapati Suresh;Chowdary Surendra;Prasad Krishna
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
17.A thermal aware 3D IC partitioning technique

机译：热敏3D IC分区技术
- 作者：Banerjee Sabyasachee;Majumder Subhashis
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Refined Partitioning;
- TSV;
- Thermal-Based-Initial Partitioning;
18.Hardware accelerator for real-time image resizing

机译：硬件加速器，用于实时调整图像大小
- 作者：Gour Pranav Narayan;Narumanchi Sujay;Saurav Sumeet;Singh Sanjay
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Bicubic Interpolation;
- Bilinear Interpolation;
- Image Resizing;
- Real Time Image Scaling;
- VLSI architecture;
19.FPGA-based implementation of M4RM for matrix multiplication over GF(2)

机译：基于FPGA的M4RM实现，用于GF（2）上的矩阵乘法
- 作者：Kumar Vivek;Kumar Vinay B.Y.;Patkar Sachin B.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
20.Design of a new high order OTA-C filter structure and its specification based testing

机译：一种新型高阶OTA-C滤波器结构的设计及其基于规范的测试
- 作者：Ghosh K.;Ray B.N.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
21.Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application

机译：超低功耗应用中使用单时钟节能绝热逻辑的时序电路设计
- 作者：Chanda M.;Chakraborty A.S.;Nag S.;Modak R.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Adiabatic logic;
- Pre-settable flip-flops;
- adiabatic counter;
- energy efficient;
- single-clock;
22.Layout-aware signal selection in reconfigurable architectures

机译：可重构架构中的布局感知信号选择
- 作者：Thakyal Prateek;Mishra Prabhat
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- FPGA;
- Layout;
- Post-Silicon Debug;
- Signal Selection;
23.A regular network of symmetric functions in quantum-dot cellular automata

机译：量子点细胞自动机中对称函数的规则网络
- 作者：Deb Arighna;Das Debesh K.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Majority Voter Gate;
- Quantum-dot cellular automata;
- Symmetric Functions;
- Unate Functions;
24.Timing-driven Steiner tree construction on uniform #x03BB;-geometry

机译：均匀λ几何上的时序驱动Steiner树构造
- 作者：Samanta Radhamanjari;Erzin Adil;Raha Soumyendu
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- #x03BB;
- -Geometry;
- Elmore De-lay;
- Interconnection networks;
- Steiner Tree;
25.Loop unrolling with fine grained power gating for runtime leakage power reduction

机译：具有细粒度电源门控的环路展开功能可减少运行时的泄漏功率
- 作者：Pyne Sumanta;Pal Ajit
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
26.VLSI implementation of novel fast confluence ICA algorithm for signal processing applications

机译：用于信号处理应用的新型快速融合ICA算法的VLSI实现
- 作者：Jayasanthi Ranjith M.E.;Muniraj N.J.R.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
27.A BDD based secure hardware design method to guard against power analysis attacks

机译：基于BDD的安全硬件设计方法可防范功耗分析攻击
- 作者：De Partha;Banerjee Kunal;Mandal Chittaranjan
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Binary Decision Dia-gram;
- Early propagation effect;
- Power analysis attack;
- Voltage scaling;
28.Cryptanalysis of Composite PUFs (Extended abstract-invited talk)

机译：复合PUF的密码分析（扩展的受邀演讲）
- 作者：Nguyen Phuong Ha;Sahoo Durga Prasad;Mukhopadhyay Debdeep;Chakraborty Rajat Subhra
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- PUF;
- Physically unclonable function;
- cryptanal-ysis;
29.UVM based STBUS verification IP for verifying SoC architectures

机译：基于UVM的STBUS验证IP，用于验证SoC架构
- 作者：Samanta Pranay;Chauhan Deepak;Deb Sujay;Gupta Piyush Kumar
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- DUT;
- STBUS;
- UVM;
- VIP;
- functional verification;
30.Deterministic seed selection and pattern reduction in Logic BIST

机译：逻辑BIST中的确定性种子选择和模式减少
- 作者：Bhakthavatchalu Ramesh;Krishnan Sreeja;Vineeth V.;Devi M.Nirmala
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- ATPG;
- DFT;
- LBIST;
- LFSR;
- MISR;
- at-speed testing;
- random patterns;
- scan chain;
- seed selection;
31.A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip

机译：3D片上网络的新递归分区组播路由算法
- 作者：Meena Narendra Kumar;Kapoor Hemangee K.;Chakraborty Shounak
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- 3D-NoC;
- Multicast routing;
- NoC;
- Recursive partitioning multicast;
32.Tunnel FET based low voltage static vs dynamic logic families for energy efficiency

机译：基于隧道FET的低压静态和动态逻辑系列可提高能源效率
- 作者：Subramanyam Kasturi;Shaik Sadulla;Vaddi Ramesh
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Energy efficiency;
- FinFET;
- Logic families;
- Steep slope devices;
- Tunnel FETs;
- Ultra low power;
33.Modelling and analysis of wireless communication over Networks-on-Chip

机译：片上网络中无线通信的建模和分析
- 作者：Kumar Apoorv;Kapoor Hemangee K.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Network on Chips;
- NoC performance analysis;
- Noxim;
- Wireless NoC;
- Wireless simulation;
- Wormhole routing;
34.Automatic real-time extraction of focused regions in a live video stream using edge width information

机译：使用边缘宽度信息自动实时提取实时视频流中的关注区域
- 作者：Singh Sanjay;Saurav Sumeet;Saini Ravi;Saini Anil K;Shekhar Chandra;Vohra Anil
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Edge Width Computation;
- FPGA Implementation;
- Focused Region Extraction;
- VLSI Architecture;
35.An analytic potential and threshold voltage model for short-channel symmetric double-gate MOSFET

机译：短沟道对称双栅MOSFET的解析电势和阈值电压模型
- 作者：Singh Yadav Vimal Kumar;Baruah Ratul Kr.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- DIBL;
- potential;
- short-channel MOSFET;
- threshold voltage roll-off;
36.An approach for efficient FIR filter design for hearing aid application

机译：用于助听器的高效FIR滤波器设计的方法
- 作者：Kotha Srinivasa Reddy;Bilaye Devendra;Jain Utkarsh;Kumar Sahoo Subhendu
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- 4:2 Compressor;
- CSD;
- FIR filter;
- HCS#x005F;
- CSD;
- Hearing aid;
37.Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors

机译：高Q可变宽度和间距，平面和3D堆叠螺旋电感器的设计和建模
- 作者：Manikandan R.R.;Rao Vanukuru Venkata Narayana;Chakravorty Anjan;Amrutur Bharadwaj
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
38.Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization

机译：基于可变厚度的步进MEMS悬臂设计的建模和仿真，用于生物传感和引入电压优化
- 作者：Parsediya Deep Kishore;Singh Jawar;Kankar Pavan Kumar
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Microcantilever in-vivo analysis;
- pull-in voltage;
39.A re-router for optimizing wire length in two-and four-layer no-dogleg channel routing

机译：一种用于优化两层和四层无折线通道布线中的电线长度的重新布线器
- 作者：Sau Swagata Saha;Pal Rajat Kumar
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Channel routing problem;
- Manhattan routing;
- No-dogleg;
- Parametric difference;
- VLSI;
- Wire length minimization;
40.Power analysis attack using neural networks with wavelet transform as pre-processor

机译：使用小波变换作为预处理器的神经网络进行功率分析攻击
- 作者：Saravanan P.;Kalpana P.;Prcethisri V.;Sneha V.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- advanced encryption standard;
- cryptography;
- machine learning;
- power analysis attack;
- side channel analysis;
- wavelet transform;
41.An FPGA implementation of image signature based visual-saliency detection

机译：基于图像签名的视觉显着性检测的FPGA实现
- 作者：Kaushik Bhavit;Saini Ravi;Saini Anil;Singh Sanjay;Mandal A.S.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Bottom-Up Approach;
- Discrete Cosine Transform;
- FPGA implementation;
- Human Vision System;
- Saliency Map;
42.An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect

机译：考虑阱邻近效应的大规模CMOS反相器经验增量延迟模型
- 作者：Dalai Bijay Kumar;Karnnan N.;Sharma Arvind;Anand Bulusu
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- CMOS inverter;
- Delta delay model;
- Timing variations;
- Well Proximity Effect (WPE);
43.A positive level shifter for high speed symmetric switching in flash memories

机译：用于闪存中高速对称开关的正电平转换器
- 作者：Sinha Rohan;Hashmi M.S.;Kumar G.Anil
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- ON resistance;
- Positive Level Shifter;
- Switching delay;
- process corners;
- threshold voltage;
- voltage stress;
44.Artificial neural network modelling of ADS designed Double Pole Double Throw switch

机译：ADS设计的双刀双掷开关的人工神经网络建模
- 作者：Majumdar Shubhankar;Zuhair Mohd.;Biswas Dhrubes
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Artificial Neural Network;
- DPDT Switch;
- Insertion Loss;
- Isolation;
- Noise Figure;
- Port Return Loss;
45.A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications

机译：适用于数字微流控生物芯片应用的45 uW 13 pJ / conv步骤7.4-ENOB 40 kS / s SAR ADC
- 作者：Das Indrajit;Sahoo Manodipan;Roy Pranab;Rahaman Hafizur
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
46.VLSI design of fast fractal image encoder

机译：快速分形图像编码器的VLSI设计
- 作者：Panigrahy Mamata;Chakrabarti Indrajit;Dhar Anindya Sundar
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- FIC;
- Morton scan;
- PIFS;
- PSNR;
47.A 32#x00D7;32 CMOS image sensor: Tested using process and temperature compensated voltage controlled current source

机译：32×32 CMOS图像传感器：使用过程和温度补偿压控电流源进行测试
- 作者：Kumar P.Saidesh;Seenivasan M.A.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Adaptive Integration time;
- CMOS Process;
- Current Source;
- Photodiode;
48.Design of tunnel FET based low power digital circuits

机译：基于隧道FET的低功耗数字电路设计
- 作者：Kamal Akhila;Bindu B.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Tunnel FET;
- Verilog-A;
- circuit simulation;
- digital circuits;
- full-adder;
- subthreshold slope;
49.An ultra low power MICS/ISM band transmitter in 0.18 #x03BC;m CMOS

机译：采用0.18μmCMOS的超低功耗MICS / ISM频段发射机
- 作者：Ghosh Amitava;Dhar Anindya S.;Halder Achintya
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Frequency Calibration;
- Frequency Shift Keying;
- One-stage ring oscillator;
- Power Amplifier;
- Switch;
- Transmitter;
- Ultra low power;
50.All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit

机译：基于马赫曾德尔干涉仪的可逆时序电路的全光学实现
- 作者：Dutta Pratik;Bandyopadhyay Chandan;Rahaman Hafizur
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Flip-Flop;
- Mach-Zehnder Interferometer (MZI);
- Optical computing;
- Reversible;
- garbage outputs;
51.Architectures and algorithms for image and video processing using FPGA-based platform

机译：使用基于FPGA的平台进行图像和视频处理的架构和算法
- 作者：Pandey J.G.;Karmakar A.;Gurunarayanan S.
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Architectures and algorithms;
- FPGA-based design;
- image and video processing;
- platform-based design;
52.A Pseudo-Deadline Based O(1) proportional share scheduler for embedded systems

机译：嵌入式系统中基于伪截止期限的ON（1）比例份额调度程序
- 作者：Ray Swarnendu;Sarkar Arnab
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Completely Fair Scheduler;
- Low Overheads;
- O(1) Scheduler;
- Proportional Share Scheduling;
53.A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV

机译：VLIW-矢量协处理器设计，用于加速OpenCV中的基本线性代数运算
- 作者：Puppala Venkata Ganapathi
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Computer Vision;
- Fused MAC;
- OpenCV;
- VLIW;
- Vector Floating Point Datapath;
54.Design of a fault tolerant low-order interleaved memory based on the concept of bubble-stack an image storage perspective

机译：基于气泡堆栈概念的容错低阶交错存储器的设计
- 作者：Das Somak;Dey Sowvik
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Memory bandwidth;
- bubble-stack;
- fault tolerance;
- field programmable gate array;
- fine grain;
- interleaved memory;
- processor utilization;
55.Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model

机译：基于窗口的峰值功率模型的粒子群优化指导多频功率感知片上系统测试调度
- 作者：Karmakar Rajit;Agarwal Aditya;Chattopadhyay Santanu
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Multifrequency testing;
- System-on-Chip Power-aware testing;
- Window-based peak power model;
56.TID effects on retention of 0.13 #x03BC;m SONOS memory cell: A device simulation approach

机译：TID对0.13μmSONOS存储单元保持力的影响：一种设备仿真方法
- 作者：Bassi Shipra;Pattanaik Manisha
- 会议名称：《18th International Symposium on VLSI Design and Test》 | 2014年
- Charge trapping;
- Data retention;
- SONOS flash memories;
- TCAD simulation;
- Total Ionizing Dose(TID);