A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications

机译：适用于数字微流控生物芯片应用的45 uW 13 pJ / conv步骤7.4-ENOB 40 kS / s SAR ADC

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In recent years Digital Micro-fluidic Bio-chips have become a suitable choice for point of care diagnostics. These devices can detect various properties of human blood by means of an optical detection technique. The data acquisition is generally done using a LED-photodiode setup working in conjunction with the biochip. The voltage signal obtained at the photodiode output needs to be converted into digital data for further processing. A low power 8 bit SAR ADC is designed for this purpose and implemented in UMC 180 nm technology. The functionality testing of the ADC is done using Spectre simulator of Cadence Analog Design Environment. The ADC consumes about 45 μWof power at 13 pJ/conv-step from a 1.8 V supply at 40 kS/s and achieves a SNDR of 46.5 dB, ENOB of 7.4 bits at a signal bandwidth of 10kHz. Mismatch analysis has been done by a set of Monte Carlo Simulations in Cadence. Even in worst case condition with 5% capacitance mismatch, the ADC achieves a SNDR of 43 dB, ENOB of 7 bits without any missing code.

机译：近年来，数字微流控生物芯片已成为护理点诊断的合适选择。这些设备可以通过光学检测技术检测人体血液的各种特性。通常使用与生物芯片配合工作的LED光电二极管设置完成数据采集。需要将在光电二极管输出处获得的电压信号转换为数字数据以进行进一步处理。为此目的设计了一个低功耗的8位SAR ADC，并以UMC 180 nm技术实现。 ADC的功能测试是使用Cadence Analog Design Environment的Spectre模拟器完成的。 ADC从40 kS / s的1.8 V电源以13 pJ / conv步进消耗约45μW功率，并在10kHz的信号带宽下实现46.5 dB的SNDR，7.4位的ENOB。失配分析已通过Cadence中的一组Monte Carlo Simulations完成。即使在电容失配率为5％的最坏情况下，ADC的SNDR也达到43 dB，ENOB为7位，而没有任何遗漏代码。

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来源
《18th International Symposium on VLSI Design and Test》|2014年|1-6|共6页
会议地点 Coimbatore(IN)
作者
Das Indrajit; Sahoo Manodipan; Roy Pranab; Rahaman Hafizur;
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作者单位

School of VLSI Technology, Indian Institute of Engineering Science and Technology, Shibpur, India;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Binary Weighted Capacitor Array; Digital Microfluidic Biochip; Low Power ADC,. SAR ADC; Low Power SAR ADC; Optical Detection;

机译：二进制加权电容器阵列；数字微流生物芯片；低功耗ADC。 SAR ADC;低功耗SAR ADC;光学检测；;

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1. A 0.5-V, 1.47- $muhbox{W}$ 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation [J] . Ha H., Lee S., Kim B., Circuits and Systems II: Express Briefs, IEEE Transactions on . 2014,第11期

机译：0.5V，1.47- $ muhbox {W} $ 40kS / s 13位SAR ADC带电容器误差补偿
2. A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator [J] . Hsieh Sung-En, Hsieh Chih-Cheng IEEE Journal of Solid-State Circuits . 2019,第6期

机译：具有低运放时域积分器的0.4V 13位270kS / s SAR-ISDM ADC
3. A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator [J] . Hsieh Sung-En, Hsieh Chih-Cheng IEEE Journal of Solid-State Circuits . 2019,第6期

机译：具有少量时域集成器的0.4V 13位270-kS / S SAR-ISDM ADC
4. A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications [C] . Das Indrajit, Sahoo Manodipan, Roy Pranab, International Symposium on VLSI Design and Test . 2014

机译：用于数字微流体Biochip应用的45 UW 13 PJ / CVIP-STEP 7.4-ENOB 40 KS / S SAR ADC
5. Conception d'un SAR-ADC de 10/13-bit à 83kS˙s-1 avec fonction de dithering =Design of a 83ks.S-1 10/13-Bit SAR-ADC with Dithering Feature [D] . Sauvé, Quentin. 2017

机译：使用抖动功能= 83ks-1的10/13位SAR-ADC设计，探测功能=设计为83ks.S-1 10/13位SAR-ADC，具有点击功能
6. A 13-bit Noise Shaping SAR-ADC with Dual-Polarity Digital Calibration [O] . Hangue Park, Maysam Ghovanloo -1

机译：具有双极性数字校准的13位噪声整形SAR-ADC
7. A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior [O] . Veldhorst, P., Goksun, George, Buter, Berry, 2009

机译：在45nm CMOS中的0.45pJ /转换步长1.2Gs / s 6b全奈奎斯特非校准闪存ADC及其缩放行为

A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications

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