A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications

机译：用于数字微流体Biochip应用的45 UW 13 PJ / CVIP-STEP 7.4-ENOB 40 KS / S SAR ADC

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In recent years Digital Micro-fluidic Bio-chips have become a suitable choice for point of care diagnostics. These devices can detect various properties of human blood by means of an optical detection technique. The data acquisition is generally done using a LED-photodiode setup working in conjunction with the biochip. The voltage signal obtained at the photodiode output needs to be converted into digital data for further processing. A low power 8 bit SAR ADC is designed for this purpose and implemented in UMC 180 nm technology. The functionality testing of the ADC is done using Spectre simulator of Cadence Analog Design Environment. The ADC consumes about 45 μWof power at 13 pJ/conv-step from a 1.8 V supply at 40 kS/s and achieves a SNDR of 46.5 dB, ENOB of 7.4 bits at a signal bandwidth of 10kHz. Mismatch analysis has been done by a set of Monte Carlo Simulations in Cadence. Even in worst case condition with 5% capacitance mismatch, the ADC achieves a SNDR of 43 dB, ENOB of 7 bits without any missing code.

机译：近年来，数字微流体生物芯片已成为护理点诊断点的合适选择。这些装置可以通过光学检测技术检测人血的各种性质。数据采集通常使用与Biochip一起工作的LED光电二极管设置完成。在光电二极管输出处获得的电压信号需要被转换成数字数据以进行进一步处理。低功耗8位SAR ADC专为此目的而设计，并在UMC 180nm技术中实现。 ADC的功能测试是使用Cadence模拟设计环境的幽灵模拟器完成的。 ADC在40 ks / s的1.8 V电源下消耗大约45μw的电源，从1.8 V电源处，实现46.5 dB的SND，在10kHz的信号带宽处为7.4位。一系列蒙特卡罗模拟在节奏中完成了不匹配分析。即使在具有5％电容不匹配的情况下最坏的情况下，ADC也可以实现43 dB的SND，eNOB为7位，没有任何丢失的代码。

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《International Symposium on VLSI Design and Test》|2014年||共6页
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Das Indrajit; Sahoo Manodipan; Roy Pranab; Rahaman Hafizur;
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中图分类大规模集成电路、超大规模集成电路;
关键词
Binary Weighted Capacitor Array; Digital Microfluidic Biochip; Low Power ADC,. SAR ADC; Low Power SAR ADC; Optical Detection;

机译：二元加权电容器阵列;数字微流体生物芯片;低功率ADC;。 SAR ADC;低功耗SAR ADC;光学检测;

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1. A 0.5-V, 1.47- $muhbox{W}$ 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation [J] . Ha H., Lee S., Kim B., Circuits and Systems II: Express Briefs, IEEE Transactions on . 2014,第11期

机译：0.5V，1.47- $ muhbox {W} $ 40kS / s 13位SAR ADC带电容器误差补偿
2. A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator [J] . Hsieh Sung-En, Hsieh Chih-Cheng IEEE Journal of Solid-State Circuits . 2019,第6期

机译：具有低运放时域积分器的0.4V 13位270kS / s SAR-ISDM ADC
3. A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator [J] . Hsieh Sung-En, Hsieh Chih-Cheng IEEE Journal of Solid-State Circuits . 2019,第6期

机译：具有少量时域集成器的0.4V 13位270-kS / S SAR-ISDM ADC
4. A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications [C] . Das Indrajit, Sahoo Manodipan, Roy Pranab, 18th International Symposium on VLSI Design and Test . 2014

机译：适用于数字微流控生物芯片应用的45 uW 13 pJ / conv步骤7.4-ENOB 40 kS / s SAR ADC
5. Conception d'un SAR-ADC de 10/13-bit à 83kS˙s-1 avec fonction de dithering =Design of a 83ks.S-1 10/13-Bit SAR-ADC with Dithering Feature [D] . Sauvé, Quentin. 2017

机译：使用抖动功能= 83ks-1的10/13位SAR-ADC设计，探测功能=设计为83ks.S-1 10/13位SAR-ADC，具有点击功能
6. A 13-bit Noise Shaping SAR-ADC with Dual-Polarity Digital Calibration [O] . Hangue Park, Maysam Ghovanloo -1

机译：具有双极性数字校准的13位噪声整形SAR-ADC
7. A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior [O] . Veldhorst, P., Goksun, George, Buter, Berry, 2009

机译：在45nm CMOS中的0.45pJ /转换步长1.2Gs / s 6b全奈奎斯特非校准闪存ADC及其缩放行为

A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications

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