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首页> 外文会议>18th International Symposium on VLSI Design and Test >A thermal aware 3D IC partitioning technique
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A thermal aware 3D IC partitioning technique

机译：热敏3D IC分区技术

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摘要

On-chip power density plays a major role in case of Highperformance VLSI circuits. 3D chips have significantly larger power densities compared to their 2D counterparts due to increased scaling of technology and also increased number of components with higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Thermal problems and limitations on inter-layer via (TSV) densities are important design constraints on three-dimensional integrated circuits (3D ICs). In this paper we introduce an algorithm where the modules with relatively high power densities are placed at the bottom layer and subsequently modules with relatively less power densities are placed on more higher layers. The temperatures of the layers vary in a non-increasing manner from the bottommost layer to the topmost layer to ensure efficient heat dissipation of the whole chip, which means we may require lesser number of heat TSVs to dissipate heat. Along with this thermal aware partitioning technique, we also tried to minimize the number of inter-layer vias (Signal TSVs) by swapping some modules across layers, in exchange of little increment in the area of the layer that has the maximum area in the circuitry. The experimental results we got are quite encouraging.
机译：片上功率密度在高性能VLSI电路中起着重要作用。与3D芯片相比，3D芯片具有更高的功率密度，这归因于技术规模的扩大以及具有更高频率和带宽的组件数量的增加。消耗的功率通常会转化为散热，从而影响芯片的性能和可靠性。热问题和层间过孔（TSV）密度的限制是三维集成电路（3D IC）的重要设计约束。在本文中，我们介绍了一种算法，其中将功率密度相对较高的模块放置在底层，然后将功率密度相对较低的模块放置在较高的层上。从最底层到最顶层，各层的温度以不增加的方式变化，以确保整个芯片的有效散热，这意味着我们可能需要较少数量的热量TSV来散热。除了这种具有热感知能力的分区技术外，我们还尝试通过跨层交换一些模块来最小化层间过孔（信号TSV）的数量，以换取电路中具有最大面积的层的面积的少量增加。我们获得的实验结果令人鼓舞。

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