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A thermal aware 3D IC partitioning technique

机译：热感知3D IC分区技术

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On-chip power density plays a major role in case of Highperformance VLSI circuits. 3D chips have significantly larger power densities compared to their 2D counterparts due to increased scaling of technology and also increased number of components with higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Thermal problems and limitations on inter-layer via (TSV) densities are important design constraints on three-dimensional integrated circuits (3D ICs). In this paper we introduce an algorithm where the modules with relatively high power densities are placed at the bottom layer and subsequently modules with relatively less power densities are placed on more higher layers. The temperatures of the layers vary in a non-increasing manner from the bottommost layer to the topmost layer to ensure efficient heat dissipation of the whole chip, which means we may require lesser number of heat TSVs to dissipate heat. Along with this thermal aware partitioning technique, we also tried to minimize the number of inter-layer vias (Signal TSVs) by swapping some modules across layers, in exchange of little increment in the area of the layer that has the maximum area in the circuitry. The experimental results we got are quite encouraging.
机译：片上功率密度在高度成功的VLSI电路的情况下起作用的主要作用。与技术缩放的缩放增加，3D芯片相比，3D芯片具有显着更大的功率密度，并且还增加了具有较高频率和带宽的组件数量增加。消耗的功率通常转换成耗散的热量，影响芯片的性能和可靠性。层间通过（TSV）密度层间的热问题和限制是三维集成电路（3D ICS）的重要设计约束。在本文中，我们介绍了一种算法，其中具有相对高功率密度的模块放置在底层处，随后将具有相对较少的功率密度的模块放置在更高的层上。层的温度以非增加的方式从最大的方式变化到最顶层，以确保整个芯片的有效散热，这意味着我们可能需要较少数量的热TSV来消散热量。与此相伴的热意识到划分技术，我们也试图通过在具有最大面积在所述电路层的区域跨层交换一些模块，在小增量的交换最小化层间导通孔（信号的TSV）的数。我们得到的实验结果非常令人鼓舞。

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