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A novel architecture for QPSK modulation based on time-mode signal processing

机译：基于时间模式信号处理的QPSK调制的新架构

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With shrinking process technology, the scale of integration has increased significantly for digital design. Therefore, the increase in operating frequency, and attempt to reduce area and power has been addressed to large extent. On the contrary, it has lesser impact on its analog counterpart and has not been able to catch up with the respective design metrics pertaining to digital design. This paper presents a new design method for Quadrature Phase Shift Keying (QPSK) modulation technique using Time Mode Signal Processing (TMSP) technique. This method uses a digital clock signal acting as the carrier signal and thus provides a digital interface at the output. A 2 bit input digital code modulates the delay of the clock and hence carries the information in it. The proposed design yields a low voltage and low power alternative to its known analog counterparts. We implemented the design using 0.18μm TSMC CMOS technology. The power supply is kept at 2V, while the carrier frequency remains 250MHz. The results for both pre and post-layout simulations yield significant improvement in layout area, power dissipation and signal-to-noise ratio (SNR) as compared to a conventional design for QPSK modulation.
机译：随着工艺技术的收缩工艺技术，数字设计的集成规模显着增加。因此，在很大程度上提出了运行频率的增加，并尝试降低面积和功率。相反，它对模拟对应物产生较小的影响，并且无法赶上与数字设计有关的各自的设计指标。本文介绍了一种使用时间模式信号处理（TMSP）技术的正交相移键控（QPSK）调制技术的新设计方法。该方法使用作用作载波信号的数字时钟信号，从而在输出处提供数字接口。一个2位输入数字代码调制时钟的延迟，因此携带信息。所提出的设计对其已知的模拟对应物产生低电压和低功率替代方案。我们使用0.18μm的TSMC CMOS技术实现了设计。电源保持在2V，而载波频率保持250MHz。与QPSK调制的传统设计相比，预先布局模拟的结果产生了显着的布局区域，功率耗散和信噪比（SNR）。

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