Effect of symmetrical underlap length on device performance of a GaN-based double gate MOSFET

机译：对称的下重叠长度对GaN基双栅MOSFET器件性能的影响

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

GaN-based double gate DG-MOSFETs have been designed and simulated in nano-scale regime for future logic-switching applications. To minimize the short-channel effects (SCEs), both gate-to-source (G-S) and gate-to-drain (G-D) lengths, symmetrical underlap length, LUN, have been extended. The underlap architectured-devices exhibit better performance due to reduction of coupling capacitance between the contacts (S-G and G-D). The value of subthreshold slope (SS) and drain induced barrier lowering (DIBL) are 62.897 mV/decade and 33.59 mV/V, respectively for an underlap length, LUN = 8 nm with a gate length, LG = 12 nm.

机译：基于GaN的双栅极DG-MOSFET已在纳米尺度下进行了设计和仿真，以用于未来的逻辑开关应用。为了最小化短沟道效应（SCE），栅极到源极（G-S）和栅极到漏极（G-D）的长度（对称的下重叠长度LUN）都已扩展。由于减小了触点（S-G和G-D）之间的耦合电容，因此底层重叠结构的器件表现出更好的性能。亚阈值斜率（SS）和漏极引起的势垒降低（DIBL）的值分别对应于重叠长度LUN = 8 nm和栅极长度LG = 12 nm的下叠层长度62.897 mV /十倍和33.59 mV / V。

著录项

来源
《2016 5th International Conference on Informatics, Electronics and Vision》|2016年|1001-1005|共5页
会议地点 Dhaka(BD)
作者
Safayet Ahmed; Md. Tanvir Hasan; Muhammad Shaffatul Islam;
展开▼
作者单位

Department of Electrical and Electronic Engineering, American Intenational Univrsity - Bangladesh (AIUB) Dhaka, Bangladesh;

Department of Electrical and Electronic Engineering, American Intenational Univrsity - Bangladesh (AIUB) Dhaka, Bangladesh;

Department of Electrical and Electronic Engineering, World University of Bangladesh (WUB), Dhaka, Bangladesh;

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Logic gates; MOSFET; Gallium nitride; Performance evaluation; Ions; Couplings;

机译：逻辑门MOSFET氮化镓性能评估离子耦合;

相似文献

外文文献
中文文献
专利

1. Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET [J] . Pardeshi H., Pati S.K., Raj G., Journal of Semiconductors . 2012,第12期

机译：下重叠和栅极长度对AlInN / GaN下重叠MOSFET器件性能的影响
2. Analog/RF Performance Investigation of Nanoscale Gate-Underlap Single and Double Gate Silicon-On-Insulator MOSFETs with High-k Stack on Spacer [J] . Singh Indra Vijay, Alam M. S. Journal of Nanoelectronics and Optoelectronics . 2015,第6期

机译：间隔器上具有高k堆栈的纳米级栅下单层和双栅绝缘体上硅MOSFET的模拟/ RF性能研究
3. Investigation of asymmetric effects due to gate misalignment, gate bias and underlap length in III-V heterostructure underlap DG MOSFET [J] . Hemant Pardeshi, Sudhansu Kumar Pati, Godwin Raj, Physica, E. Low-dimensional systems & nanostructures . 2012,第3期

机译：研究III-V型异质结构下叠式DG MOSFET中由于栅极未对准，栅极偏置和下叠长度引起的不对称效应
4. Effect of symmetrical underlap length on device performance of a GaN-based double gate MOSFET [C] . Safayet Ahmed, Md. Tanvir Hasan, Muhammad Shaffatul Islam International Conference on Informatics, Electronics and Vision . 2016

机译：对称下划线长度对基于GaN的双栅MOSFET器件性能的影响
5. Process-based compact modeling and analysis of silicon-on-insulator CMOS devices and circuits, including double-gate MOSFETs. [D] . Chiang, Meng-Hsueh. 2001

机译：对绝缘体上硅CMOS器件和电路（包括双栅MOSFET）的基于过程的紧凑建模和分析。
6. Performance of arsenene and antimonene double-gate MOSFETs from first principles [O] . Giovanni Pizzi, Marco Gibertini, Elias Dib, -1

机译：首要原理的砷和锑双栅极MOSFET的性能
7. High tolerance to gate misalignment in low voltage gate-underlap double gate MOSFETs [O] . Kranti, Abhinav, Armstrong, Alastair 2008

机译：低压栅极叠底双栅极MOSFET对栅极失准的高容限
8. Device Performance and Reliability Improvements of AlGaN/GaN/Si MOSFET Using Defect-Free Gate Recess and Laser Annealing. [R] . Wallace, R. M. 2015

机译：利用无缺陷栅极凹陷和激光退火改善alGaN / GaN / si mOsFET的器件性能和可靠性。

Effect of symmetrical underlap length on device performance of a GaN-based double gate MOSFET

摘要

著录项

相似文献

相关主题

期刊订阅