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首页> 外文会议>Advances in Electronic Packaging 2005 pt.A >THERMAL BASED OPTIMIZATION OF FUNCTIONAL BLOCK DISTRIBUTIONS IN A NON-UNIFORMLY POWERED DIE
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THERMAL BASED OPTIMIZATION OF FUNCTIONAL BLOCK DISTRIBUTIONS IN A NON-UNIFORMLY POWERED DIE

机译：非均匀功率模具中基于功能块的热优化

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Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 x 4 and 6x6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.
机译：微处理器的功能，复杂性和性能不断增长。当前一代的微处理器将诸如逻辑和二级（L2）高速缓存之类的功能组件集成到微处理器体系结构中。随着时钟速度的增加和指令执行时间的减少，微处理器的功能集成使微处理器具有更好的性能。但是，这种集成为微处理器的热设计和管理带来了一层复杂性。功能集成的直接结果是，微处理器上的功率图高度不均匀，并且假设整个芯片表面的热通量均不成立。本文的目的是通过优化均匀供电功能块的分布来最小化封装的热阻。为了对硅芯片上的非均匀功耗进行建模，将芯片表面积分为4 x 4和6x6矩阵，矩阵空间表示具有恒定热通量的不同功能块。最后，使用FEM代码对功能块之间的相对位置进行优化，以使结温Tj最小。该分析对功能块的重新分配没有任何限制。因此可以找到最佳的Tjmax降低。实际上（以后），必须对任何两个（或更多）功能块的最大间隔进行限制，以满足电气时序和计算性能的要求。然后针对任何数量的功能块，建议基于热的最佳分配的设计准则。商业有限元代码ANSYS®用于此分析。

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