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Synthesis and properties of Si and SiGe/Si nanowires

机译:Si和SiGe / Si纳米线的合成与性能

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The fabrication of semiconductor nanowires, in which composition, size and conductivity can be controlled in both the radial and axial direction of the wire is of interest for fundamental studies of carrier confinement as well as nanoscale device development. In this study, group IV semiconductor nanowires, including Si, Ge and Si_xGe_(1-x) alloy nanowires were fabricated by vapor-liquid-solid (VLS) growth using gaseous precursors. In the VLS process, gold is used to form a liquid alloy with Si and Ge which, upon supersaturation, precipitates a semiconductor nanowire. Nanoporous alumina membranes were used as templates for the VLS growth process, in order to control the diameter of the nanowires over the range from 45 nm to 200 nm. Intentional p-type and n-type doping was achieved through the addition of either trimethylboron, diborane or phosphine gas during nanowire growth. The electrical properties of undoped and intentionally doped silicon nanowires were characterized using field-assisted assembly to align and position the wires onto pre-patterned test bed structures. The depletion characteristics of back-gated nanowire structures were used to determine conductivity type and qualitatively compare dopant concentration. SiGe and SiGe/Si axial heterostructure nanowires were also prepared through the addition of germane gas during VLS growth. The Ge concentration in the wires was controllable over the range from 12 % to 25% by varying the inlet GeH_4/SiH_4 ratio.
机译:对于载流子限制以及纳米级器件开发的基础研究而言,在半导体纳米线的制造中,可以在金属丝的径向和轴向上控制其成分,大小和导电率,是令人感兴趣的。在这项研究中,使用气态前驱物通过汽-液-固(VLS)生长制造了包括Si,Ge和Si_xGe_(1-x)合金纳米线的第IV组半导体纳米线。在VLS工艺中,金用于与Si和Ge形成液态合金,一旦过饱和,就会沉淀出半导体纳米线。为了将纳米线的直径控制在从45 nm到200 nm的范围内,将纳米多孔氧化铝膜用作VLS生长过程的模板。通过在纳米线生长期间添加三甲基硼,乙硼烷或磷化氢气体,实现了有意的p型和n型掺杂。使用场辅助组件对未掺杂和有意掺杂的硅纳米线的电学特性进行了表征,以将线对准并放置在预先构图的测试台结构上。背栅纳米线结构的耗尽特性用于确定导电类型并定性比较掺杂剂浓度。还通过在VLS生长期间添加锗烷气体制备了SiGe和SiGe / Si轴向异质结构纳米线。通过改变入口GeH_4 / SiH_4的比例,可控制导线中的Ge浓度在12%至25%的范围内。

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