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Physical Timing Verification of Subwavelength-Scale Designs -Part I: Lithography Impact on MOSFETs

机译：亚波长规模设计的物理和时序验证-第一部分：光刻对MOSFET的影响

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Subwavelength lithography at low contrast, or low-k_1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a 'fact-of-life' for the designer implementing nanometer-scale designs for the foreseeable low-k_1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less fidelity in comparison to the designer's desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer's physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k_1 decreases to unprecedented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k_1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC, alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systematic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more cost-effective application of RET.
机译：低对比度或低k_1因子的亚波长光刻技术对设计，设计分析和设计验证技术提出了新要求。这些技术必须考虑到在这个时代由布局相关的设计到硅的图案形成过程所导致的固有的物理电路特征失真。即使存在复杂的分辨率增强技术（RET），这些失真也是不可避免的，对于在可预见的低k_1未来实施纳米级设计的设计人员来说，这是“生活事实”。结果是，与设计者所需的布局相比，制造的硅特征形状和尺寸通常要比前代设计的保真度要低得多，并且设计者必须考虑在几何公差范围内有显着差异的设计。传统（Mead-Conway起源）的所见即所得（所见即所得）设计方法，假设设计人员的物理电路元件形状与实际制造的IC上的相应形状相比是准确的，并使用设计规则来验证令人满意的制造符合性，既是互连寄生负载计算的输入，又是用于性能仿真的晶体管模型的输入。但是，随着k_1下降到空前的水平，这些假设变得越来越糟糕-随之而来的是图案化特征失真和制造良率失效模式的增加。本文探索了一种用于纳米级设计的新范例，该范例将关键的低k_1平版印刷效果的更高级模型集成到设计流程中，以提高产量和性能验证的准确性。我们首先对复杂的32位加法器电路设计进行分析，以确定由于光学邻近效应而导致电路中每个MOSFET的栅极长度，宽度和形状变化的系统变化。仿真所预测的所有物理门的尺寸随后被合并到电路仿真模型和网表（原理图）中，并用于计算关键参数屈服因子的变化，例如电路行为中的时序和功耗。这些功能性后果产生了与功能和参数成品率有关的可制造性公差要求，而不仅仅是物理可制造性。然后，我们探索通过RET对这些变形进行系统校正而产生的功能属性和可制造性方面的改进，包括：基于仿真驱动的基于模型的OPC，交替孔径PSM（altPSM）和altPSM + OPC。这种分析只是将光刻效果纳入制造设计（DFM）方案的系统方法的一个维度。这些优势有望大大改善硅签核验证，预测性能和良率分析，以及更具成本效益的RET应用。

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