NBTI Improvement for pMOS by Cl-contained 1st Oxidation in 20A/65A Dual Nitrided Gate-oxide of 0.13um CMOS technology

机译：在0.13um CMOS技术的20A / 65A双氮化栅极氧化物中含Cl的第一氧化处理对pMOS的NBTI改进

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A new method is demonstrated in this paper for improving the NBTI lifetime on pMOS by >3X for I/O (65A) transistors and >2X for core (20A) transistors by using Chlorine (Cl) contained 1st gate oxidation in an advanced dual gate oxide 0.13um CMOS technology. The improvement appears related to the residual Si-Cl bonds on the surface of core and I/O transistor areas (from the Cl-contained 1st oxidation). The transistor beta (as measured by I_(dsat)/(V_g-V_t)~2 at saturation mode) is improved (～10%) on pMOS and degraded slightly (～3%) on nMOS as an evidence for supporting this mechanism

机译：本文展示了一种新方法，该方法可通过在高级双栅极中使用含氯（Cl）的第一栅极氧化技术，将p / MOS（65A）晶体管的NBTI寿命提高> 3倍，将核心（20A）晶体管的NBTI寿命提高> 2倍。氧化物0.13um CMOS技术。改善似乎与铁芯和I / O晶体管区域表面上残留的Si-Cl键有关（来自含Cl的第一氧化）。晶体管beta（在饱和模式下由I_（dsat）/（V_g-V_t）〜2测得）在pMOS上提高了（〜10％），在nMOS上稍微降低了（〜3％），以证明支持这种机制

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来源
《Design and Process Integration for Microelectronic Manufacturing II》|2003年|p.180-187|共8页
会议地点 Santa Clara CA(US)
作者
Ching-Chen Hao; Min-hwa Chi; Chao-Chi Chen; Hung-Jen Lin; Yu-Fang Lin; C. H. Hsieh; C. H. Lee; K. H. Chang; H. T. Wu; Chih-Heng Shen;
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Nan-Ke North Rd, Science-Based Industrial Park, Tainan, Taiwan 741, R.O.C;

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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
NBTI; pMOSFET; nitrided; gate-oxide;

机译：NBTI; pMOSFET;氮化;栅氧化物;

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外文文献
专利

1. PMOS-switching dual-path charge pump in standard twin-well CMOS technology [J] . Jung-Chan Lee, Yeonbae Chung International journal of electronics . 2010,第3a4期

机译：采用标准双阱CMOS技术的PMOS开关双路电荷泵
2. PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies [J] . Zhiyu Liu, Kursun V. IEEE transactions on very large scale integration (VLSI) systems . 2007,第12期

机译：低于65nm CMOS技术的仅PMOS睡眠开关双阈值电压Domino逻辑
3. Sub-1/4-/spl mu/m dual-gate CMOS technology using in-situ doped polysilicon for nMOS and pMOS gates [J] . Okazaki Y., Kobayashi T. IEEE Transactions on Electron Devices . 1995,第9期

机译：低于1/4 / splμm/ m的双栅极CMOS技术，使用用于nMOS和pMOS栅极的原位掺杂多晶硅
4. NBTI Improvement for pMOS by Cl-contained 1st Oxidation in 20A/65A Dual Nitrided Gate-oxide of 0.13um CMOS technology [C] . Ching-Chen Hao, Min-hwa Chi, Chao-Chi Chen, Conference on design and process integration for microelectronic manufacturing . 2003

机译：在20A / 65A双氮化栅极氧化物中的CL载的第1氧化氧化物通过0.13um CMOS技术改善PMOS的NBTI改善
5. Oxide reliability improvement through nitridation technology in VLSI CMOS and nonvolatile memory devices. [D] . Zhou, Zhixu. 1999

机译：通过VLSI CMOS和非易失性存储器件中的氮化技术提高了氧化物的可靠性。
6. PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies [O] . Zhiyu Liu, Student Member, Volkan Kursun 2016

机译：低于65纳米CmOs技术的pmOs专用睡眠开关双阈值电压多米诺逻辑

NBTI Improvement for pMOS by Cl-contained 1st Oxidation in 20A/65A Dual Nitrided Gate-oxide of 0.13um CMOS technology

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