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Simulation based data processing using repeated pattern identification

机译：使用重复模式识别的基于仿真的数据处理

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In typical integrated circuits (IC) designs, the final layout generally contains a lot of repeated patterns. Many of these repetitions are captured by the layout hierarchy. That is, the layout contains many cells that are each repeatedly placed in many locations with different transformation. Effective use of such repetition information in the computation intensive operations such as model-based optical proximity correction (OPC), verification, or contour generation, can lead to significant performance improvement. However, in many other occasions, such repetition information is not directly available. For example, if the layout is flattened, then all the hierarchy that captures the repetition information is lost. Even in hierarchical layout, a cell can contain repeated geometries or patterns. In order for the application to take advantage of such property, a mechanism to efficiently capture such repetition information is necessary. In this paper, we consider the model-based applications that have a unique property, which allows us to find different geometrical patterns that are equivalent in principle for simulation purpose. We introduce a proximity-based pattern identification method which aims at recognizing the maximum amount of repetition in the layout. This method not only captures repeated or symmetric geometries that are present from either the flattening of the hierarchy or within a cell itself, but also finds symmetries within the geometries themselves. The method also finds partial repetitions of geometries that are not completely identical or symmetric. Ideally, these "equivalent" patterns will eventually carry the same processing results with miniscule variations small enough to be ignored for the application. For this reason, it is sufficient to run the computationally expensive model-based operations for one of the pattern and carry the result to the rest of the patterns of the same family. Doing so reduces the problem size as well as the amount of data that requires processing. The total processing tune therefore can be dramatically reduced. We demonstrate the method by using OPC as a test example. We show the level of problem size reduction and job run time reduction due to the specific nature of different layouts.
机译：在典型的集成电路（IC）设计中，最终布局通常包含许多重复的图案。这些重复中有许多是由布局层次结构捕获的。即，布局包含许多单元，每个单元以不同的变换重复放置在许多位置。在诸如基于模型的光学邻近校正（OPC），验证或轮廓生成之类的计算密集型操作中有效使用此类重复信息可导致显着的性能改进。但是，在许多其他情况下，此类重复信息不是直接可用的。例如，如果布局被展平，则捕获重复信息的所有层次结构都会丢失。即使在分层布局中，单元也可以包含重复的几何形状或图案。为了使应用程序利用这种特性，必须有一种有效捕获这种重复信息的机制。在本文中，我们考虑具有独特属性的基于模型的应用程序，这使我们能够找到原则上等效于仿真目的的不同几何图案。我们介绍一种基于邻近度的模式识别方法，旨在识别布局中的最大重复次数。此方法不仅可以捕获由于层次结构扁平化而出现的重复或对称几何形状，也可以捕获像元本身内部的几何形状，而且可以发现几何形状本身内的对称性。该方法还发现不完全相同或对称的几何形状的部分重复。理想情况下，这些“等效”模式最终将携带相同的处理结果，并且其微小变化应小到足以被应用程序忽略。因此，对于一个模式运行足够昂贵的基于模型的运算并将结果带到同一族的其他模式就足够了。这样做可以减少问题的大小以及需要处理的数据量。因此，总的处理量可以大大减少。我们通过使用OPC作为测试示例来演示该方法。由于不同布局的特定性质，我们显示了减少问题大小和减少作业时间的级别。

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