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首页> 外文会议>Design and Process Integration for Microelectronic Manufacturing II >Creation and Verification of Phase Compliant SoC Hard IP for the Fabless COT Designers
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Creation and Verification of Phase Compliant SoC Hard IP for the Fabless COT Designers

机译：为无工厂COT设计人员创建和验证符合相位要求的SoC硬IP

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摘要

As the semiconductor industry has begun volume production of sub-wavelength geometries, technologies such as Optical Proximity Correction (OPC) and Phase-Shift Masks (PSM) have become main stream. One of these approaches, Alternating PSM (AltPSM), has been adopted by leading edge semiconductor companies to meet high-performance IC manufacturing requirements. As part of a complete production flow for these high-performance processes, it is required that System-on-Chip (SoC) Hard Intellectual Property (IP) cores be "phase compliant". Only through phase compliance, the fabless Customer Owned Tooling (COT) semiconductor market is enabled to leverage the benefits of AltPSM technology. Traditional design rules cannot be used alone to create and verify phase compliant designs. This paper proposes a new methodology to create and verify phase-compliant SoC IP. The methodology was implemented and verified on Virage Logic's Single Port SRAM compilers for UMC's 0.13-micron MPU, high-performance CMOS logic process based on 70-nm transistor gates, which are manufactured utilizing patented AltPSM technology from Numerical Technologies, Inc. Examples of certain areas of the layout before and after phase compliance are presented. The timing characterization data is also included to show that the performance (speed) of the memory layouts was enhanced by 20% over regular 0.13 micron process. The paper concludes with some general remarks on how this methodology will be impacted as we move to 65nm node.
机译：随着半导体行业开始批量生产亚波长几何形状，诸如光学邻近校正（OPC）和相移掩模（PSM）之类的技术已成为主流。领先的半导体公司已采用其中一种方法，即交替PSM（AltPSM）来满足高性能IC制造要求。作为这些高性能过程的完整生产流程的一部分，要求片上系统（SoC）硬知识产权（IP）内核必须“符合阶段”。只有通过阶段合规性，无晶圆厂客户拥有的工具（COT）半导体市场才能够利用AltPSM技术的优势。传统设计规则不能单独用于创建和验证阶段兼容设计。本文提出了一种新的方法来创建和验证阶段兼容的SoC IP。该方法已在Virage Logic的用于UMC的0.13微米MPU，基于70纳米晶体管栅极的高性能CMOS逻辑工艺的单端口SRAM编译器上实施和验证，该编译器使用了NUMERIC TECHNOLOGY，INC。的专利AltPSM技术制造。介绍了阶段合规前后的版图区域。时序特征数据也包括在内，以表明与常规的0.13微米工艺相比，存储器布局的性能（速度）提高了20％。本文以一些一般性的结论作为结束语，说明了当我们转向65nm节点时该方法将如何受到影响。

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