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首页> 外文会议>Conference on design and process integration for microelectronic manufacturing >Creation and Verification of Phase Compliant SoC Hard IP for the Fabless COT Designers
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Creation and Verification of Phase Compliant SoC Hard IP for the Fabless COT Designers

机译：Fabless COT设计人员的阶段兼容SoC硬IP的创建和验证

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As the semiconductor industry has begun volume production of sub-wavelength geometries, technologies such as Optical Proximity Correction (OPC) and Phase-Shift Masks (PSM) have become main stream. One of these approaches, Alternating PSM (AltPSM), has been adopted by leading edge semiconductor companies to meet high-performance IC manufacturing requirements. As part of a complete production flow for these high-performance processes, it is required that System-on-Chip (SoC) Hard Intellectual Property (IP) cores be "phase compliant". Only through phase compliance, the fabless Customer Owned Tooling (COT) semiconductor market is enabled to leverage the benefits of AltPSM technology. Traditional design rules cannot be used alone to create and verify phase compliant designs. This paper proposes a new methodology to create and verify phase-compliant SoC IP. The methodology was implemented and verified on Virage Logic's Single Port SRAM compilers for UMC's 0.13-micron MPU, high-performance CMOS logic process based on 70-nm transistor gates, which are manufactured utilizing patented AltPSM technology from Numerical Technologies, Inc. Examples of certain areas of the layout before and after phase compliance are presented. The timing characterization data is also included to show that the performance (speed) of the memory layouts was enhanced by 20% over regular 0.13 micron process. The paper concludes with some general remarks on how this methodology will be impacted as we move to 65nm node.
机译：由于半导体行业已经开始储存亚波长几何形状，因此诸如光学接近校正（OPC）和相移掩模（PSM）的技术已成为主流。这些方法之一交替的PSM（ALTPSM），是由前沿半导体公司采用的，以满足高性能IC制造要求。作为这些高性能流程的完整生产流程的一部分，需要片上系统（SoC）硬性知识产权（IP）核心是“阶段兼容”。只有通过阶段合规性，无晶型客户拥有的工具（COT）半导体市场才能使ALTPSM技术的好处。传统的设计规则不能单独使用以创建和验证阶段兼容的设计。本文提出了一种创建和验证阶段符合阶段的SOC IP的新方法。该方法得到了实现，并且在Virage Logic公司的单端口SRAM编译器UMC的0.13微米MPU验证，高性能的CMOS逻辑工艺基于70nm的晶体管栅极，其利用专利AltPSM技术从数字技术的某些公司实施例中制造前阶段达标后布局的区域呈现。还包括定时表征数据，以表明，在常规0.13微米工艺中，存储器布局的性能（速度）增强了20％。本文的结论是关于如何在移动到65nm节点时如何影响该方法的一般性言论。

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