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Low Cost Wafer Bumping of GaAs Wafers

机译：GaAs晶片的低成本晶片凸点

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The microelectronics industry has implemented a significant number of process technologies tornaccomplish the various packaging and backend operations. These technologies have been successfullyrnimplemented at a number of contract manufacturing companies and also licensed to many of thernsemiconductor manufacturers and foundries. The largest production volumes for these technologies arernfor silicon based semiconductors which are based on either aluminum or copper interconnect metallurgy.rnThe direct transfer of these technologies to compound semiconductor devices, like GaAs, LiTaO3, andrnGaN, is limited due to a number of technical compatibility issues and several perceived compatibilityrnissues [1-4].rnFrom a technical standpoint, many of these high end devices contain fragile air bridges, gold bond pads,rncavities & trenches, and unique bulk material properties which are sensitive to many of the mechanicalrnand chemical processes associated with many of the standard packaging operations using for siliconrnwafers. Special care must be taken to ensure that there is no mechanical stress put on the wafer duringrnany of the handling operations associated with deposition of the UBM, solder bumping, wafer thinning,rndicing, and die sort. In addition, many chemicals used for resist stripping, metal etching, and solderrnfluxing will react with some of the materials on these compound semiconductor devices.rnFrom a perception standpoint, companies which are processing large numbers of silicon basedrnsemiconductor wafers in their packaging and backend facilities, are reluctant to process many of theserncompound semiconductors because there is a perceived issue with cross contamination between therndifferent wafer materials. Companies are not willing to risk their current business of processing siliconrnwafers by introducing these new materials into their existing process flow.rnThe strategy in this study is to protect all structures and surfaces with a resist or film as part of each steprnin the process. This protects the wafer from mechanical and chemical damage; and at the same timernprotects sensitive fab processes from contamination by the compound semiconductor.
机译：微电子工业已经实现了大量的工艺技术来完成各种封装和后端操作。这些技术已在许多合同制造公司成功实施，并已授权给许多半导体制造商和铸造厂。这些技术的最大产量是基于铝或铜互连冶金的硅基半导体。由于多种技术兼容性问题，将这些技术直接转移到化合物半导体器件（如GaAs，LiTaO3和rnGaN）中受到限制。以及一些可察觉的兼容性问题[1-4] .rn从技术的角度来看，这些高端设备中的许多设备都包含易碎的气桥，金键焊盘，空腔和沟槽以及独特的块状材料特性，这些特性对许多相关的机械和化学过程敏感与许多用于硅晶圆的标准包装操作有关。在进行任何与UBM沉积，焊料隆起，晶圆变薄，切割和芯片分类相关的处理操作期间，必须格外小心，以确保晶圆上没有机械应力。此外，用于抗蚀剂剥离，金属蚀刻和助焊剂的许多化学药品也会与这些化合物半导体器件上的某些材料发生反应。从感知的角度来看，正在包装和后端设施中加工大量硅基半导体晶圆的公司，由于在不同的晶片材料之间存在交叉污染，因此人们不愿意处理许多新型化合物半导体。公司不愿意通过将这些新材料引入其现有工艺流程来冒着目前加工硅晶片的风险。这项研究的策略是在工艺的每个步骤中使用抗蚀剂或薄膜保护所有结构和表面。这样可以保护晶圆免受机械和化学损害。同时保护敏感的制造工艺不受化合物半导体的污染。

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