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首页> 外文会议>Electrochemical Society Meeting and International Symposium on ULSI Process Integration III; 20030428-20030502; Paris; FR >PROCESS STRATEGY FOR BUILT-IN RELIABILITY OF CU DAMASCENE INTERCONNECT SYSTEM FOR 0.13UM-NODE AND BEYOND
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PROCESS STRATEGY FOR BUILT-IN RELIABILITY OF CU DAMASCENE INTERCONNECT SYSTEM FOR 0.13UM-NODE AND BEYOND

机译：CU DAMASCENE互连系统内置可靠性的过程策略，适用于0.13UM节点和更高端

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摘要

The process parameters for Cu damascene interconnect were investigated in order to design the built-in reliability for EM, SM and TDDB. Precise patterning and residue-free etching were the fundamental items for the confirmation of reliability. The optimization of step coverage inside via and the increase of adhesion strength to Cu and dielectrics were indispensable for barrier metal. Further, not only the grain size control but also the stress control of Cu was necessary in order to improve SM reliability. Additionally, the surface control of Cu/dielectric surface from Cu-CMP to dielectric deposition, such as the freedom from damage and the elimination of CuO were also effective for the improvement of TDDB reliability. Because the reliability of Cu metallization was strongly affected by these parameters, the pre-fundamental evaluation and feasibility check were important to introduce new technologies and materials for 0.13um-node and beyond.
机译：研究了铜镶嵌互连的工艺参数，以设计EM，SM和TDDB的内置可靠性。精确的图案化和无残留蚀刻是确认可靠性的基本条件。对于阻挡金属，优化通孔内部的台阶覆盖率以及增加对Cu和电介质的附着强度是必不可少的。此外，为了提高SM的可靠性，不仅需要控制晶粒尺寸，还需要控制Cu的应力。另外，从Cu-CMP到介电沉积的Cu /介电表面的表面控制，例如不受损伤和消除CuO，对于提高TDDB的可靠性也是有效的。由于这些参数极大地影响了铜金属化的可靠性，因此，进行基础前的评估和可行性检查对于引入适用于0.13um及更高节点的新技术和材料非常重要。

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