Performance analysis of 3-D asymmetric junctionless double gate MOSFET

机译：3-D非对称无结双栅极MOSFET的性能分析

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摘要

In this work, performance analysis of sub nanometer asymmetric junctionless transistor has been studied. Lateral offset is present between the gates in the double gate structure. A comprehensive device characteristic including potential variations, drain current variations, transconductance and capacitance were analyzed. A 3D device has been designed for the simulation study using TCAD.

机译：在这项工作中，已经研究了亚纳米非对称无结晶体管的性能分析。在双栅极结构中的栅极之间存在横向偏移。分析了器件的综合特性，包括电势变化，漏极电流变化，跨导和电容。已经为使用TCAD的仿真研究设计了3D设备。

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来源
《International Conference on Energy, Communication, Data Analytics and Soft Computing》|2017年|1391-1395|共5页
会议地点 Chennai(IN)
作者
Mustafizur Rahman Hazarika; Nipanka Bora;
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作者单位

Nano Electronics and VLSI Design Laboratory Dept. of Electronics Engineering North Eastern Hill University Shillong-793022 India;

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关键词
Logic gates; MOSFET; Capacitance; Doping; Threshold voltage; Transconductance;

机译：逻辑门MOSFET;电容;掺杂门槛电压；跨导;

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4. Performance Analysis of 3-D Asymmetric Junctionless Double Gate MOSFET [C] . Mustafizur Rahman Hazarika, Nipanka Bora International Conference on Energy, Communication, Data Analytics and Soft Computing . 2017

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5. Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs [D] . Laha, Soumyasanta 2015

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7. Performance analysis of ultrathin junctionless double gate vertical MOSFETs [O] . K. E. Kaharudin, Z. A. F. M. Napiah, F. Salehuddin, 2019

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Performance analysis of 3-D asymmetric junctionless double gate MOSFET

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