Abstract: TCAD simulation is very important for DUV lithography process development and control. Traditional lithography process engineering has relied on short-loop and pilot-lot experiments to understand the effects of particular process control factors. However, experiments are very expensive, and the complexity of lithographic patterns and processes is such that we must often resort to computational simulation. The availability, accuracy, and ease of use of lithography simulation are essential to the semiconductor industry. In this paper we present a methodology for DUV lithography simulator tuning by resists profile matching. A global optimization procedure is used to efficiently extract the correct values of the important fitting parameters by matching the simulated resist profiles to measured data. Results for a DUV lithography process are presented. !8
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