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首页> 外文会议>International VLSI multilevel interconnection conference;VMIC >CHEMICAL MECHANICAL PLANARIZATION OF ILD DEVICE WAFERS USING CERIA OXIDE SLURRY
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CHEMICAL MECHANICAL PLANARIZATION OF ILD DEVICE WAFERS USING CERIA OXIDE SLURRY

机译：氧化铈浆液对ILD设备晶片的化学机械平面化

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With major price fluctuations of DRAM devices the semiconductor industry is investigating several processes to improve process yield and throughput to help reduce DRAM costs per die. One method the semiconductor industry is investigating to increase throughput is by using a high removal rate oxide process. In general this requires a specific type of slurry. Presently the industry consensus is to use a ceria based slurry for high removal rate oxide processes. The throughput advantage here is to reduce present process times for planarizing ILD device structures from four to one minute. Theoretically this would increase the throughput by almost a factor of 4. Present drawbacks of this slurry are process stability. This point is highlighted in figure 1 in which we have plotted the removal rate and WIWNU (%) as a function of the run number, for a total of 112-polished wafer, using 49-pt @ 5-mm edge exclusion. Here a run consists of polishing 6 wafers simultaneously. Here the average removal rate is 5020-A/min and a WIWNU -1σof 4.78-%. In addition, the initial removal rate starts off at about 4500-A/min and settles to about 5200-A/min. This results in a (MAX. - MIN.)/2~*Ave. of 10-%, which just meets present semiconductor fabrication specifications. This process is based on a fairly high relative linear velocity and a low down force pressure of 250-ft/min and 5-psi, respectively. This same process recipe was used to planarize oxide test wafers and the results are shown in figure 2. Here we plot the step height as a function of the square size structures after the one-minute planarization step. The total amount of TEOS material removed was ～10-k Angstroms and was carried out in one minute. For structures ≤ 1-mm the Degree Of Planarity (DOP) was ～1 and less then one for structures > 1-mm. In this paper we describe the experimental details carried out in this work as well as slurry handling and CMP issues that need investigating in order to make high removal rate oxide processes using ceria based slurry production worthy.
机译：随着DRAM设备价格的大幅波动，半导体行业正在研究几种工艺，以提高工艺良率和吞吐量，以帮助降低每个芯片的DRAM成本。半导体工业正在研究增加产量的一种方法是使用高去除率的氧化物工艺。通常，这需要特定类型的浆料。目前，业界共识是将二氧化铈基浆料用于高去除率的氧化物工艺。这里的吞吐量优势是将用于平面化ILD器件结构的当前处理时间从四分钟减少到一分钟。从理论上讲，这将使生产率提高近四倍。该浆料的当前缺点是工艺稳定性。这一点在图1中突出显示，其中我们绘制了去除率和WIWNU（％）与运行次数的函数关系，使用49点@ 5毫米边缘排除法对总共112块抛光过的晶片进行了绘制。这里的运行包括同时抛光6个晶片。在这里，平均去除速度为5020-A / min，WIWNU-1σ为4.78％。另外，初始去除速率开始于约4500A / min，并稳定至约5200A / min。这导致（MAX。-MIN。）/ 2〜* Ave。刚好满足当前半导体制造规范的10％。此过程分别基于相当高的相对线速度和250英尺/分钟和5磅/平方英寸的低向下压力。使用相同的工艺配方对氧化物测试晶片进行平面化，结果如图2所示。在这里，我们绘制了一分钟平面化步骤后，台阶高度与方形结构的关系。去除的TEOS材料总量约为10k埃，在一分钟内完成。对于≤1 mm的结构，平面度（DOP）为〜1，而对于> 1-mm的结构，其小于1。在本文中，我们描述了这项工作中进行的实验细节，以及需要研究的浆料处理和CMP问题，以使使用二氧化铈基浆料生产的高去除率氧化物工艺值得进行。

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