• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>International Conference on Field Programmable Logic and Applications >A NOVEL FPGA DESIGN ACCELERATION METHODOLOGY SUPPORTED BY A UNIQUE RP PLATFORM FOR FAST AND EASY SYSTEM DEVELPOMENT
【24h】

A NOVEL FPGA DESIGN ACCELERATION METHODOLOGY SUPPORTED BY A UNIQUE RP PLATFORM FOR FAST AND EASY SYSTEM DEVELPOMENT

机译：一种独特的RP平台支持的新型FPGA设计加速方法，用于快速简便的系统开发

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Today the development of modern electronic systems is characterized by an increasing complexity of products and competitive pressure. This demands new procedures and technologies for the development process to increase the quality of development by reduction of time and costs. Especially in this area Rapid Prototyping (RP) systems are used to accelerate the development process. Basically the commercial RP systems use dedicated hardware to support the huge variety of different I/O interface functions for logical sensor and actuator adaptation. Every I/O card only provides a single functionality with multiple inputs or outputs. Their internal architecture follow traditional structures and so only supports strict forward modeling - e.g. no subsystems are possible. In case of a large number of distinct interfaces, a wide range of different I/O cards is necessary along with the need of sufficient card slots. This is ineffective with respect to flexibility and costs.
机译：今天，现代电子系统的发展是越来越多的产品复杂性和竞争力。这需要通过减少时间和成本来提高发展过程的新程序和技术。特别是在该领域，快速原型（RP）系统用于加速开发过程。基本上，商业RP系统使用专用硬件来支持逻辑传感器和执行器适应的各种不同I / O接口功能。每个I / O卡只提供具有多个输入或输出的单个功能。他们的内部架构遵循传统结构，因此只支持严格的前进建模 - 例如没有子系统是可能的。在大量不同的界面的情况下，需要多种不同的I / O卡以及需要足够的卡槽。对于灵活性和成本无效。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号