How to improve void performance in wafer bumping

机译：如何提高晶圆凸点的空洞性能

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Void of solder joint can be considered to be one of the main defects in electronic assembly. The existence of void will influence not only the reliability of solder joint, but also the electrical, mechanical and thermal properties of solder joint. X-ray is the traditional method to analyze solder void. The inspection criteria to void are subjective, different customers have different requirements to the void performance of the product. Although the theory of forming void is known, different cases need different actions to get optimized void performance. The main objective of this paper is to study how much the application process can impact the void performance independently. The process parameters investigated in this study mainly include printing parameter effect, reflow profile effect and heating mechanism effect on void formation of solder joint.

机译：焊点空隙可被认为是电子装配中的主要缺陷之一。空隙的存在不仅会影响焊点的可靠性，还会影响焊点的电，机械和热性能。 X射线是分析焊锡空隙的传统方法。废品的检验标准是主观的，不同的客户对产品的废品性能有不同的要求。尽管形成空洞的理论是众所周知的，但不同的情况需要采取不同的措施才能获得最佳的空洞性能。本文的主要目的是研究应用程序在多大程度上可以独立影响空隙性能。本文研究的工艺参数主要包括印刷参数效应，回流曲线效应和加热机理对焊点空隙形成的影响。

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《IEEE Electronics Packaging Technology Conference》|2014年|743-746|共4页
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Zhang Ruifen; Yap Kong Tat; Yam Lip Huei; Dexter R.;
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electric properties; mechanical properties; semiconductor device reliability; solders; thermal properties; electrical properties; electronic assembly; heating mechanism on; inspection criteria; mechanical properties; printing parameter effect; reflow profile effect; solder joint reliability; thermal properties; void performance improvement; wafer bumping; Heat transfer; Heating; Metals; Ovens; Printing; Soldering; Solvents;

机译：电学性能;机械性能;半导体器件的可靠性;焊料;热学性能;电学性能;电子装配;加热机理;检验标准;机械性能;印刷参数效应;回流曲线效应;焊点可靠性;热学性能;无效性能改善;晶圆碰撞;传热;加热;金属;烤箱;印刷;焊接;溶剂;

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专利

1. Increasing performance and speed with wafer bumping [J] . JACK BOGDANSKI, PAUL A. MAGILL, BOYD ROGERS, Advanced Packaging . 2000,第6期

机译：晶圆凸点提高性能和速度
2. Stencil Printing Behavior of Lead-Free Sn-3Ag-0.5Cu Solder Paste for Wafer Level Bumping for Sub-100 jum Size Solder Bumps [J] . Santosh Kumar, Sabuj Mallik, Ndy Ekere Metals and Materials International . 2013,第5期

机译：小于100微米尺寸锡块的晶圆级焊接用无铅Sn-3Ag-0.5Cu锡膏的模具印刷行为。
3. Pb-free Sn/3.5Ag wafer-bumping process and UBM (under bump metallurgy) study [J] . S. Y. Jang, J. Wolf, O. Ehrmann, Microsystem technologies . 2001,第5a6期

机译：无铅Sn / 3.5Ag凸块工艺和UBM（凸点冶金）研究
4. How to improve void performance in wafer bumping [C] . Zhang Ruifen, Yap Kong Tat, Yam Lip Huei, IEEE Electronics Packaging Technology Conference . 2014

机译：如何提高晶圆碰撞中的空隙性能
5. Electrical characterization and performance analysis of wafer scale lossy interconnection lines for wafer scale integration systems. [D] . Kim, Jaeseok. 1988

机译：晶圆级集成系统的晶圆级有损互连线的电气特性和性能分析。
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How to improve void performance in wafer bumping

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