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Composite attribute method and software to interlock semiconductor product design and manufacturing yield

机译:联锁半导体产品设计与制造良率的复合属性方法与软件

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Semiconductor product design content changes in recent technology nodes significantly changes yield even when the same die size is maintained. A method and software has been developed and implemented in IBM's 32 and 14nm ASIC products to track yield impacts related to content change throughout the design process so that unexpected cost impacts can be avoided.
机译:即使保持相同的芯片尺寸,最新技术节点中半导体产品设计内容的变化也会显着改变良率。已经在IBM的32和14纳米ASIC产品中开发并实现了一种方法和软件,以跟踪与整个设计过程中内容更改相关的良率影响,从而可以避免意外的成本影响。

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