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首页> 外文会议>IEEE International System-on-Chip Conference >Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors
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Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors

机译：基于标准单元库的布局表征和10nm门 - 全周（GAA）晶体管的功率分析

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Gate-all-around (GAA) nanowire transistor is promising for continuing scaling down the feature size of transistors beyond sub-10nm because it provides the gate with better controllability over the channel by wrapping around. In this paper, the device model for 10nm gate length conventional GAA (C-GAA) and junctionless GAA (JL-GAA) are extracted based on the TCAD simulation. The layout design of GAA transistors are characterized for different sizing methods. Liberty-formatted standard cell libraries are constructed by appropriately sizing pull-up and pull-down networks of each logic cell. Based on the library, power densities of 10nm technology node C-GAA and JL-GAA are analyzed under benchmark circuits in comparing with 7nm FinFET technology. Experimental results show that the vertical C-GAA transistor can achieve 28% area reduction and the horizontal C-GAA transistor can reduce 29% power consumption comparing with other C-GAA geometries. The power density of JL-GAA circuits can reach above the limit of air cooling and thermal management techniques are needed for JL-GAA circuits.
机译：栅极 - 全方位（GaA）纳米线晶体管很有希望继续缩小超出子10nm之外的晶体管的特征尺寸，因为它通过包裹在沟道上提供具有更好的可控性的栅极。本文基于TCAD仿真提取了10nm栅极长度传统GaA（C-GaA）和结镀Gaa（JL-GaA）的装置模型。 GaA晶体管的布局设计的特征在于不同尺寸的方法。 Liberty格式的标准单元库由每个逻辑小区的提升和下拉网络进行适当大化。基于图书馆，在与7nm FinFET技术相比，在基准电路下分析了10nm技术节点C-Gaa和JL-Gaa的功率密度。实验结果表明，垂直C-GAA晶体管可以实现28％的面积减少，水平C-GAA晶体管可以减少与其他C-GaA几何形状比较的29％的功耗。 JL-GAA电路的功率密度可达到高于空气冷却极限，并且JL-GAA电路需要热管理技术。

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