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Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist

机译：采用自感应塌陷写入辅助功能的22nm FinFET低功耗（22FFL）技术中的550mV SRAM设计

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Exceptionally low minimum operating voltage (V_MIN) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm^{2 high-density bitcell (HDC) and 32Mb array of 0.107μm^{2 high-current bitcell (HCC) achieve the 95^{th percentile V_MIN of 505mV and 450mV respectively across a temperature range of -10°C to 95°C. A self-induced collapse (SIC) write assist integrated into the 6-T HDC SRAM bitcell array enables 110mV V_MIN reduction relative to an unassisted array at the 95^{th percentile with negligible power overhead.}}}}

机译：极低的最低工作电压（V _{MIN
）SRAM阵列已在22nm FinFET低功耗技术（22FFL）上进行了演示[1]。通过优化未掺杂的SRAM晶体管并应用行业标准的写辅助技术，0.087μm的16Mb阵列
^{2
高密度位元（HDC）和0.107μm的32Mb阵列
^{2
大电流位元（HCC）达到95
^{第
百分位数V
_{MIN
在-10°C至95°C的温度范围内分别为505mV和450mV。集成到6-T HDC SRAM位单元阵列中的自感应崩溃（SIC）写辅助功能可实现110mV V
_{MIN
相对于95的无辅助阵列减少
^{第
百分位的功率开销可忽略不计。}}}}}}}

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《IEEE Symposium on VLSI Technology》|2018年|151-152|共2页
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作者
Daeyeon Kim; Jami Wiedemer; Pramod Kolar; Ayush Shrivastava; Jinal Shah; Satyanand Nalam; Gwanghyeon Baek; Xiaofei Wang; Zheng Guo; Eric Karl;
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Silicon carbide; Random access memory; Power measurement; Voltage measurement; Frequency measurement; Area measurement; Transistors;

机译：碳化硅;随机存取存储器;功率测量;电压测量;频率测量;面积测量;晶体管;

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专利

1. A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications [J] . Chang Tsung-Yung Jonathan, Chen Yen-Huei, Chan Wei-Min, IEEE Journal of Solid-State Circuits . 2021,第1期

机译：高密度和低VMIN应用的金属耦合和电荷共享写入电路方案的高密度和电荷共享辅助电路方案的5nm 135 Mb SRAM。
2. A 16 nm 128 Mb SRAM in High- src="/images/tex/243.gif" alt="kappa "> Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications [J] . Chen Y.-H., Chan W.-M., Wu W.-C., Solid-State Circuits, IEEE Journal of . 2015,第1期

机译：具有高 src =“ / images / tex / 243.gif” alt =“ kappa”> 具有写入辅助功能的金属门FinFET技术的16 nm 128 Mb SRAM低VMIN应用的电路
3. 10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV VMIN Reduction With Negligible Active Power Overhead [J] . Zheng Guo, Jami Wiedemer, Yusung Kim, . 2021,第1期

机译：10-NM SRAM设计使用栅极调制的自塌方写入辅助，可实现175 MV VMIN减少，具有可忽略的电力开销
4. Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist [C] . Daeyeon Kim, Jami Wiedemer, Pramod Kolar, IEEE Symposium on VLSI Technology . 2018

机译：22nm FinFET低功耗（22FFL）技术的Sub-550mV SRAM设计，具有自诱导的折叠写辅助
5. Leakage Power Attack-resilient Designs of a SRAM Cell in 7NM FinFET Technology [D] . Chen, Kangqi. 2019

机译：采用7NM FinFET技术的SRAM单元的漏电攻击恢复设计
6. Power optimized variation aware dual-threshold SRAM cell design technique [O] . Aminul Islam, Mohd Hasan 2011

机译：功耗优化的变化感知双阈值SRAM单元设计技术
7. Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology [O] . Rajendra Prasad S, B K Madhavi, Prof. K Lal Kishore 2011

机译：基于CNTFET的32nm工艺低写功耗sRam单元设计

Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist

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