This paper will first focus on the theory of guard rings and the importance of understanding for internal and external latchup. This will be followed by electrical characterization and the demonstrates integration of parameterized cell guard ring structures in a Cadence™ based design methodology for the construction of ESD structures, I/O design, and latchup for radio frequency (RF) CMOS and Silicon Germanium technology. The importance of the guard ring p-cell allows for evaluation of internal and external latchup, and the ability to verify the presence of the guard ring for whole chip design checking, verification and synthesis will be discussed.
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