VLSI-Oriented Architecture for Two''s Complement Serial-Parallel Multiplication without Speed Penalty

机译：VLSI导向架构为两个'的补充串行 - 并行乘法而无速度罚款

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A serial-parallel multiplier computes a product by multiplying a parallel input and a serial (or online) input. Serial-parallel multipliers are frequently used in digital communication systems, digital signal processing, on-line computing applications, and embedded computing and communication systems. In this paper, a VLSI-oriented, size-efficient two''s complement serial-parallel multiplication architecture is proposed. In addition to its smaller size, it is also suitable for VLSI implementation because it consists of modularized logic cells and locally interconnected signals. According to the analysis results for 2- to 32- bit multiplication, the proposed architecture requires up to 30 percent smaller size without speed penalty compared to the previous architecture.

机译：串行乘法器通过乘以并行输入和串行（或在线）输入来计算产品。串行并行乘法器通常用于数字通信系统，数字信号处理，在线计算应用和嵌入式计算和通信系统。在本文中，提出了一种VLSI定向的尺寸有效的两个'补充串行并行乘法架构。除了较小的尺寸外，它还适用于VLSI实现，因为它包括模块化逻辑单元和局部互连的信号。根据分析结果的2至32位乘法，拟议的架构需要较小的尺寸高达30％，而与以前的架构相比，没有速度惩罚。

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《International Conference on Computational Science and its Applications》|2007年||共5页
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Moh Sangman; ICCSA;
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中图分类 TP39-53;
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4. VLSI-Oriented Architecture for Two''s Complement Serial-Parallel Multiplication without Speed Penalty [C] . Moh, Sangman . 2007

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5. A high-speed modular multiplier architecture based on modified Montgomery's multiplication algorithm. [D] . Magadi, Anand Shivashankaraiah. 2002

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6. Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications [O] . Md Selim Hossain, Ehsan Saeedi, Yinan Kong -1

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8. Serial-parallel multiplication in Galois fields [R] . Lin, Shu 1987

机译：伽罗瓦域中的串并行乘法

VLSI-Oriented Architecture for Two''s Complement Serial-Parallel Multiplication without Speed Penalty

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