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首页> 外文会议>Optical Microlithography XI >Evaluation of phase-edge phase-shifting mask for sub-0.18-um gate patterns in logic devices
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Evaluation of phase-edge phase-shifting mask for sub-0.18-um gate patterns in logic devices

机译：逻辑器件中0.18um以下栅极图案的相边缘相移掩模评估

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Abstract: The speed of logic device is mainly dependent on gate length. To achieve process margin (DOF, E/T, etc.) and minimize On Chip Variation (OCV) of logic gate with sub 0.18 mm design rule, the need for phase-edge PSM technology that has the advantages of minimum resolution and Critical Dimension (CD) control has been increased. In this paper, performance and feasibility of phase-edge PSM technology were investigated. Using phase-edge PSM and positive resist process at DUV wavelength ($lambda equals 248 nm), the possibility of 0.10 micrometer logic gate patterning was confirmed and 0.18 micrometer gate lines with DOF larger than 1.0 micrometer and plus or minus 6% CD variation were obtained. And design rules for phase-edge layout generation were extracted. Then the possibility of layout generation by the extracted design rules and layout conversion tool was confirmed. Also, the feasibility of mask CD uniformity and phase uniformity, and alignment between phase-edge mask and normal chrome (Cr) mask was investigated and confirmed. Considering lithographic performance and process feasibility, phase-edge PSM technology is a very promising method for patterning sub 0.18 micrometer gate in logic devices. !4
机译：摘要：逻辑器件的速度主要取决于门长度。为了实现工艺裕度（DOF，E / T等）并通过低于0.18 mm的设计规则将逻辑门的片上差异（OCV）降至最低，需要具有最小分辨率和临界尺寸优势的相沿PSM技术（CD）控制已增加。本文研究了相位边缘PSM技术的性能和可行性。使用DPS波长的相位边缘PSM和正性抗蚀剂工艺（λlambda等于248 nm），确定了0.10微米逻辑门图案的可能性，并且DOF大于1.0微米且正负CD偏差为0.18微米的栅线被确定为获得。并提取了相边缘布局生成的设计规则。然后确定了通过提取的设计规则和布局转换工具生成布局的可能性。此外，研究并确认了掩模CD均匀性和相位均匀性以及相边缘掩模和普通铬（Cr）掩模之间的对准的可行性。考虑到光刻性能和工艺可行性，相边缘PSM技术是一种用于对逻辑器件中0.18微米以下栅极进行构图的非常有前途的方法。 ！4

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