首页> 外文会议>Physics and technology of high-k materials 9 >Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization Of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies

【24h】

Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization Of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies

机译：基于电压斜坡应力的应力与压力测试方法，用于表征CMOS技术的基于Hf的高k /金属栅叠层

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

Traditionally, the reliability of gate oxides is mostly evaluated using a Constant Voltage Stress, CVS, based stress-and-sense methodology, in which a constant stress voltage is interrupted to quantify the degradation. In this paper, we discuss the use of a Voltage-Ramp Stress, VRS, based stress-and-sense method in which the stress voltage is ramped at a constant rate and degradation is quantified by interrupting the VRS at increasingly higher stress voltages. The two methods are used and compared for dielectric breakdown and bias temperature instability measurements using high-k/metal gate stacks. It is shown that the two methods can be used interchangeably, producing very similar reliability assessments. It is shown that the VRS method, however, has distinct advantages over a CVS approach. It is fast and 'foolproof, providing reliable information on the voltage acceleration without any prior knowledge on the dynamics of the degradation. The use of a VRS is therefore well suited for monitoring reliability parameters during gate stack and process development, and during device optimization, where large variations in the reliability parameters are common.

机译：传统上，栅极氧化物的可靠性通常使用基于恒压应力（CVS）的应力传感方法来评估，其中中断恒定的应力电压以量化退化。在本文中，我们讨论了基于电压加应力（VRS）的应力和传感方法的使用，其中应力电压以恒定速率倾斜，并且通过在越来越高的应力电压下中断VRS来量化退化。使用这两种方法进行比较，并使用高k /金属栅叠层对介电击穿和偏置温度不稳定性进行测量。结果表明，两种方法可以互换使用，产生非常相似的可靠性评估。结果表明，与CVS方法相比，VRS方法具有明显的优势。它快速且“万无一失”，可提供有关电压加速的可靠信息，而无需事先了解退化的动态。因此，VRS的使用非常适合在浇口堆栈和工艺开发期间以及在设备优化期间监视可靠性参数，在这些情况下，可靠性参数的变化很大。

著录项

来源
《Physics and technology of high-k materials 9》|2011年|p.337-348|共12页
会议地点 Boston MA(US);Boston MA(US)
作者
E. Cartier; A. Kerber; S. Krishnan; B. Linder; T. Ando; M. M. Frank; K. Choi; V. Narayanan;
展开▼
作者单位

IBM, T.J. Watson Research Center, Yorktown Heights, NY 10598;

GLOBALFOUNDRIES, T.J. Watson Research Center, Yorktown Heights, NY 10598;

IBM Semiconductor Research and Development Center (SRDC), T.J. Watson Research Center, Yorktown Heights, NY 10598, USA;

IBM, T.J. Watson Research Center, Yorktown Heights, NY 10598;

IBM, T.J. Watson Research Center, Yorktown Heights, NY 10598;

IBM, T.J. Watson Research Center, Yorktown Heights, NY 10598;

GLOBALFOUNDRIES, T.J. Watson Research Center, Yorktown Heights, NY 10598;

IBM, T.J. Watson Research Center, Yorktown Heights, NY 10598;

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类半导体技术;
关键词

相似文献

外文文献
中文文献
专利

1. Fast Wafer-Level Stress-and-Sense Methodology for Characterization of Ring-Oscillator Degradation in Advanced CMOS Technologies [J] . Kerber Andreas, Wan Xinggong, Liu Yang, Electron Devices, IEEE Transactions on . 2015,第5期

机译：用于表征先进CMOS技术中环形振荡器性能下降的快速晶圆级应力检测方法
2. Impact of Failure Criteria on the Reliability Prediction of CMOS Devices With Ultrathin Gate Oxides Based on Voltage Ramp Stress [J] . A. Kerber, T. Pompl, M. Rohner, IEEE Electron Device Letters . 2006,第7期

机译：失效准则对基于电压斜坡应力的超薄栅氧化物CMOS器件可靠性预测的影响
3. Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- $k$ Stacks [J] . Kerber A., Krishnan S. A., Cartier E. A. Electron Device Letters, IEEE . 2009,第12期

机译：用于金属门/高$ k $堆栈的偏置温度不稳定性测试的电压斜坡应力
4. Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization Of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies [C] . E. Cartier, A. Kerber, S. Krishnan, International Symposium on High Dielectric Constant and Other Dielectric Materials for Nanoelectronics and Photonice . 2011

机译：基于电压斜坡应力基于CMOS技术的HF基高k /金属栅极堆栈的可靠性表征的应力 - 义应力 - 检测试验方法
5. Electrical and material characteristics of hafnium-based multi-metal high-k gate dielectrics for future scaled CMOS technology: Physics, reliability, and process development. [D] . Rhee, Se Jong. 2005

机译：基于future的多金属高k栅极电介质的电气和材料特性，可用于未来的规模化CMOS技术：物理，可靠性和工艺开发。
6. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs [O] . H. Hussin, N. Soin, M. F. Bukhori, -1

机译：栅堆叠结构和工艺缺陷对32 nm工艺节点PMOSFET中NBTI可靠性的高k介电依赖性的影响
7. Hf-based high-K gate dielectric and metal gate stack for advanced CMOS devices [O] . JOO MOON SIG 2006

机译：基于Hf的高K栅极电介质和金属栅极叠层，用于高级CMOS器件

Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization Of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies

摘要

著录项

相似文献

相关主题

期刊订阅