Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

机译：基于FPGA中部分动态重配置的现代容错架构

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Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

机译：介绍了旨在将容错系统设计方法开发到FPGA平台中的活动。描述了部分重新配置的基本原理以及基于部分动态重新配置和三重模块冗余或双工系统的容错体系结构。还介绍了几种使用在线检查器进行错误检测的体系结构，这些体系结构可启动故障单元的重新配置过程。展示了将容错体系结构修改为部分可重配置模块以及在容错系统设计中使用部分动态重配置的主要优点。所有展示的架构都经过了相互比较，并在带有Virtex5的ML506开发板上针对不同类型的RTL数字组件证明了其完整的功能。

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来源
《Proceedings of the IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems》|2010年|p.173-176|共4页
会议地点 Vienna(AT)
作者
Straka M.; Kastil J.; Kotasek Z.;
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作者单位

Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic;

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会议组织
原文格式 PDF
正文语种 eng
中图分类基本电子电路;
关键词
FPGA; architecture; duplex; fault tolerant; on-line checker; partial reconfiguration; triple modular redundancy;

机译：FPGA;架构;双工;容错;在线检查器;部分重配置;三重模块冗余;

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2. A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration [J] . Alexandros Vavousis, Andreas Apostolakis, Mihalis Psarakis Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2013,第6期

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3. A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs [J] . Gonsalves Martins Victor Manuel, Cechelero Villa Paulo Ricardo, Travessini Rodrigo, Microelectronics & Reliability . 2018,第APRa期

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4. Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs [C] . Straka Martin, Kastil Jan, Kotasek Zdenek Proceedings of the IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems . 2010

机译：基于FPGA中部分动态重配置的现代容错架构
5. Application mapping for platform FPGAs with partial dynamic reconfiguration. [D] . Banerjee, Sudarshan. 2007

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7. TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs [O] . C. Bolchini, A. Miele, M. Santambrogio 2007

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8. On-Line Testing and Reconfiguration of Field Programmable Gate Arrays (FPGAs) for Fault-Tolerant (FT) Applications in Adaptive Computing Systems (ACS) [R] . Abramovici, M. , Emmert, J. M. , Stroud, C. E. 2002

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Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

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