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Copper Electrodeposition Parameters Optimization for Through-Silicon Vias Filling

机译：硅通孔填充的铜电沉积参数优化

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For years, the effectiveness of the Damascene process has allowed the semiconductor industry to successfully keep the pace with the aggressive scaling of Moore's law. However, ever increasing costs have raised the need for alternative technologies bringing advantages in terms of performance gain, time to market and cost competitiveness. Thus, 3D chip stacking technologies have now become a field of extensive research. As for the Damascene process (1,2), Through Silicon Vias (TSV) technology involves a "superfilling" copper electrodeposition step promoted by organic additives. However, the specificity of the TSV structures, high aspect-ratios and micrometric-scale Via depth (3-5), implies modifications in term of chemistry, equipment and electroplating parameters. Indeed, due to the important volume of the cavities, both the diffusion of the metallic and organic species along the Vias and their renewal, near the wafer surface, have a huge impact on the process efficiency. Therefore, electrolyte flux must be optimized to favor the species transport towards the via bottom. Similarly, several other parameters need to be adapted to this particular geometry. Thus, the influence of four process parameters -current density, process time, substrate rotation and accelerator concentration - on the via filling of 150 μm via depth presenting an aspect-ratio of 2, has been investigated. Firstly, the process parameter effects on the deposition mechanism have be evaluated by cyclic voltammetry and chrono-potentiometry experiments, carried-out on a planar electrode. Secondly, we have determined the impact of each parameter on the via filling with a particular emphasis on the defect (void) generation. The aim of these measurements is to compare the results obtained from the via filling trials in order to determine, such as for the Damascene process (1), the correlation between these two type of experiments. Thus, the purpose of this study is to optimize the process window for each parameter and possibly generalize these results to other vias geometries.
机译：多年以来，大马士革工艺的有效性使半导体行业能够成功地跟上摩尔定律的不断扩展。但是，不断增长的成本增加了对替代技术的需求，这些替代技术需要在性能提升，上市时间和成本竞争力方面带来优势。因此，3D芯片堆叠技术现在已经成为广泛研究的领域。至于大马士革工艺（1,2），通过硅通孔（TSV）技术涉及有机添加剂促进的“超填充”铜电沉积步骤。但是，TSV结构的特殊性，高长宽比和微米级的通孔深度（3-5）暗示着化学，设备和电镀参数的修改。确实，由于空腔的体积很大，金属和有机物质沿通孔的扩散以及晶片表面附近的更新都对工艺效率产生巨大影响。因此，必须优化电解质通量以有利于物质向通孔底部的传输。同样，其他几个参数也需要适应此特定几何形状。因此，研究了四个工艺参数-电流密度，工艺时间，基板旋转和加速剂浓度-对150μm的过孔深度（纵横比为2）的过孔填充的影响。首先，已通过在平面电极上进行的循环伏安法和计时电位法实验评估了工艺参数对沉积机理的影响。其次，我们确定了每个参数对通孔填充的影响，并特别强调了缺陷（空洞）的产生。这些测量的目的是比较从通孔填充试验获得的结果，以便确定（例如，对于镶嵌工艺（1））这两种类型的实验之间的相关性。因此，本研究的目的是针对每个参数优化工艺窗口，并可能将这些结果推广到其他通孔几何形状。

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