New virtual substrate concept for vertical MOS transistors

机译：垂直MOS晶体管的新虚拟衬底概念

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We propose a new concept of thin SiGe virtual substrates in which the interactions of point defects with dislocations play a key role. Being purposely introduced in the thin SiGe buffer layers during their metastable growth, point defects promote the relaxation of strain. Firstly, they cause dislocations to climb which helps to annihilate threading dislocation arms with opposite Burgers vectors. Secondly, condensation of point defects results in prismatic dislocation loops inside the layers which avoids nucleation from the surface sites. As a consequence, point defects reduce the density of existing threading dislocations and prevent the generation of new ones. This solution should allow the formation of virtual substrates with thin relaxed SiGe buffer layers and low threading dislocation density. In this paper, we explain how point defects can be injected using modified MBE process techniques. These techniques utilize either the injection of low energy Si~+ ions or super-saturation of point defects resulting from very low temperature growth.

机译：我们提出了一种薄的SiGe虚拟衬底的新概念，其中点缺陷与位错的相互作用起着关键作用。在硅锗薄缓冲层的亚稳生长过程中，有目的地将其引入，点缺陷促进了应变的松弛。首先，它们导致位错上升，这有助于消除具有相反Burgers向量的线程错位臂。其次，点缺陷的凝结导致各层内部形成棱柱状的位错环，从而避免了表面部位的形核。结果，点缺陷降低了现有螺纹错位的密度并阻止了新的螺纹错位的产生。该解决方案应允许形成具有薄的松弛SiGe缓冲层和低穿线位错密度的虚拟衬底。在本文中，我们解释了如何使用改进的MBE工艺技术注入点缺陷。这些技术要么利用低能Si〜+离子的注入，要么利用非常低的温度增长导致的点缺陷过饱和。

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来源
《Thin films epitaxial growth and nanostructures》|1998年|p.319-322|共4页
会议地点 Strasbourg(FR)
作者
Erich Kasper; Klara Lyutovich; Matthias Bauer; Michael Oehme;
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原文格式 PDF
正文语种 eng
中图分类一般工业技术;
关键词
Virtual substrate; Thin relaxed SiGe buffer layer; Point defects; Ion bombardment; Very low temperature growth; Threading dislocations;

机译：虚拟底物；薄的松弛SiGe缓冲层；点缺陷；离子轰击；温度增长极低；螺纹脱位;

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1. Demonstration of vertically-ordered h-BN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors on Si substrate [J] . Matthew Whiteside, Subramaniam Arulkumaran, Geok Ing Ng Materials Science and Engineering . 2021,第Auga期

机译：Si衬底上的垂直有序的H-BN / AlGaN / GaN金属 - 绝缘体 - 半导体高电子迁移率晶体管的示范
2. Leakage-Reduction Design Concepts for Low-Power Vertical Tunneling Field-Effect Transistors [J] . Electron Device Letters, IEEE . 2010,第6期

机译：低功率垂直隧穿场效应晶体管的减少泄漏设计概念
3. Effect of threading dislocation in an AlN nucleation layer and vertical leakage current in an AlGaN/GaN high-electron mobility transistor structure on a silicon substrate [J] . Yamaoka Yuya, Ubukata Akinori, Yano Yoshiki, Semiconductor science and technology . 2019,第3期

机译：硅衬底上的AlN成核层中的螺纹位错和AlGaN / GaN高电子迁移率晶体管结构中的垂直泄漏电流的影响
4. New virtual substrate concept for vertical MOS transistors [C] . Erich Kasper, Klara Lyutovich, Matthias Bauer, E-MRS conference on thin films epitaxial growth and nanostructures . 1998

机译：垂直MOS晶体管的新虚拟基板概念
5. Compact modeling of Silicon Carbide (SIC) Vertical Junction Field Effect Transistor (VJFET) in PSpice using Angelov model and PSpice simulation of analog circuit building blocks using SIC VJFET model. [D] . Purohit, Siddharth. 2006

机译：使用Angelov模型在PSpice中对碳化硅（SIC）垂直结场效应晶体管（VJFET）进行紧凑建模，并使用SIC VJFET模型对PSpice模拟电路构建模块进行仿真。
6. Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices [O] . Demetrio Logoteta, Gianluca Fiori, Giuseppe Iannaccone -1

机译：作为后CMOS器件基于石墨烯的横向异质结构晶体管表现出比基于石墨烯的垂直晶体管更好的固有性能
7. SiGe virtual substrate HMOS transistor for analogue applications [O] . K. Michelakisa, S. Despotopoulosa, V. Gasparia, 2015

机译：用于模拟应用的siGe虚拟衬底HmOs晶体管

New virtual substrate concept for vertical MOS transistors

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