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Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology.

机译：通过晶片键合技术制造的异质结构集成III-V半导体。

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摘要

Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances.; Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported.; Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies.; Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.
机译：将先进的微电子，光子和微机械器件（包括纳米级器件）集成到三维结构中，已成为实现用于电子和生物技术应用的先进微集成系统的关键问题。晶圆键合（晶圆融合）被认为是将不匹配的材料和设备集成到芯片级的最有前途的技术之一。不匹配的微或纳米器件在芯片上集成的主要问题之一是在不同长度尺度（包括纳米尺度）上的材料兼容性和界面结构，以及与器件的电子，光学和机械性能的结构关系。因此，在本论文的第一部分，系统地研究了晶圆键合半导体如GaAs，InP和GaN的界面微观结构。已经确定了界面形态，化学性质，位错结构和晶片键合工艺之间的关系。还分析了n型和p型多数和少数载流子在不同晶片键合的界面结处的电子输运行为，重点研究了电性能和来自不同退火工艺的界面微结构的时间相关性。此外，已经研究了晶片旋转对准对n-n和p-n结的电学特性的影响。还报道了在不同的退火条件下，不同排列时n-n结的界面电导率与p-n结的理想因子的定量关系。其次，还通过晶片退火工艺，界面断裂能和剪切强度之间的相关性，仔细分析了直接键合的GaAs，InP和GaN半导体的粘附性，机械可靠性和晶片可粘合性，以及它们的界面微失效模型，和微故障机制。基于界面电导率和微观形貌的时间测量，对退火引起的界面转变过程进行了动力学和热力学分析。最后，已经证明了结合使用低温生长的非晶α-（Ga，As）材料和晶片键合技术在GaAs衬底上制造GaSb半导体以潜在地形成绝缘体上GaSb的可行性。

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  • 作者

    Shi, Fang Frank.;

  • 作者单位

    University of Illinois at Urbana-Champaign.;

  • 授予单位 University of Illinois at Urbana-Champaign.;
  • 学科 Engineering Materials Science.; Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 106 p.
  • 总页数 106
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 工程材料学;无线电电子学、电信技术;
  • 关键词

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