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Tomography as a metrology technique for semiconductor manufacturing.

机译:层析成像技术是半导体制造的一种计量技术。

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This dissertation is concerned with exploring the feasibility of a class of sensors which provide temporally and spatially resolved wafer state information during semiconductor manufacturing. The common theme shared by this class of sensors is that they are based on Electrical Impedance Tomography (EIT). EIT is a non-destructive in vivo imaging technique principally used in medical applications.; The basic idea of Electrical Impedance Tomography is to image the conductivity distribution in the interior of a conductive object by performing simple electrical measurements on the periphery of the object. In a semiconductor manufacturing context, physical and chemical effects during semiconductor manufacturing can induce a change in conductivity in the interior of a wafer. EIT techniques can be used to infer these conductivity changes. In turn, these changes can be related to the physical and chemical effects using appropriate models.; In this thesis, we first discuss the status quo of metrology methods in use in the semiconductor manufacturing industry. This discussion is followed by a thorough introduction to Electrical Impedance Tomography. We then argue that Electrical Impedance Tomography can be a compelling technique to obtain spatially and time-resolved wafer state information during wafer processing. To illustrate these ideas, we design and analyze two EIT based sensors for use during semiconductor manufacturing.; Our first sensor is a device to measure etch rates or film thicknesses. We have designed, fabricated and tested this sensor. We use standard EIT techniques to estimate the conductivity distribution of a thin film of conductive polysilicon across a wafer. The estimated conductivity distribution can, in turn, be related to the thickness of the polysilicon film from first principles. Differential thickness measurements from our prototype etch rate sensor correlate very well with optical thickness measurements.; Next, we propose a novel EIT based sensor which can provide temporal and spatial wafer surface potential information during plasma processing. Our design relies on a resistive network containing discrete transduction elements whose conductivity is modulated by the variable of interest. To assess our idea, we performed simulation studies on a prototype sensor which uses depletion mode NMOSFETs as transduction elements. We have obtained promising simulation results with this novel EIT based metrology technique.
机译:本文涉及探索一类传感器的可行性,该类传感器在半导体制造过程中提供时间和空间分辨的晶片状态信息。此类传感器的共同主题是,它们基于电阻抗层析成像(EIT)。 EIT是一种主要用于医学应用的非破坏性的体内成像技术。电阻层析成像的基本思想是通过对对象外围进行简单的电测量来对导电对象内部的电导率分布进行成像。在半导体制造的背景下,半导体制造期间的物理和化学作用会引起晶片内部的电导率变化。 EIT技术可用于推断这些电导率变化。反过来,这些变化可以与使用适当模型的物理和化学效应有关。在本文中,我们首先讨论了在半导体制造业中使用的计量方法的现状。讨论之后,将详细介绍电阻抗层析成像。然后,我们认为电阻抗层析成像技术可能是一种引人注目的技术,可在晶圆加工过程中获得空间和时间分辨的晶圆状态信息。为了说明这些想法,我们设计并分析了两个基于EIT的传感器,供半导体制造期间使用。我们的第一个传感器是一种测量蚀刻速率或膜厚度的设备。我们已经设计,制造和测试了该传感器。我们使用标准的EIT技术来估算整个晶圆上的导电多晶硅薄膜的电导率分布。根据第一原理,估计的电导率分布又可以与多晶硅膜的厚度有关。我们的原型蚀刻速率传感器的差分厚度测量值与光学厚度测量值非常相关。接下来,我们提出了一种基于EIT的新型传感器,该传感器可以在等离子体处理过程中提供时间和空间的晶圆表面电势信息。我们的设计依赖于电阻网络,该网络包含离散的换能元件,其电导率由目标变量调节。为了评估我们的想法,我们对使用耗尽型NMOSFET作为转导元件的原型传感器进行了仿真研究。通过这种新颖的基于EIT的计量技术,我们获得了令人鼓舞的仿真结果。

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