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Switching noise and timing and characteristics in nanoscale integrated circuits.

机译：纳米级集成电路中的开关噪声，时序和特性。

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摘要

Continuous progress in the design and manufacturing of integrated circuits (ICs) has enabled the integration of more than two billion transistors on the same die with clock frequencies well above several gigahertz. These improvements have triggered the era of system-on-chip (SoC) and system-in-package (SiP), drastically changing the classical understanding of noise in complex ICs. Traditionally, device noise has been the primary concern for analog ICs while digital ICs have typically been considered to be relatively immune to noise. This situation has changed significantly due to denser integration and faster signal transition times. Specifically, switching noise has become a primary design criterion for both mixed-signal and high performance synchronous digital ICs.;Voltage fluctuations on the power/ground nodes of a circuit, i.e., power/ground noise, is a type of switching noise affecting both mixed-signal and digital ICs. A methodology is proposed to accurately estimate the worst case power/ground noise in an inductive power/ground distribution network with a decoupling capacitor. In mixed-signal ICs, power/ground noise affects the highly sensitive analog/RF blocks through the monolithic substrate, degrading critical performance parameters such as gain, bandwidth, dynamic range, total harmonic distortion, and phase noise. Several approaches are presented to efficiently model and alleviate substrate noise coupling in mixed-signal ICs. The proposed analysis process determines the noise characteristics of a circuit, thereby identifying appropriate noise isolation techniques. A methodology is also proposed to reduce noise by incorporating noise-aware standard cells. The proposed methodologies and algorithms are validated with industrial circuits, exhibiting significant improvement in computational efficiency while maintaining sufficient accuracy in the noise voltage. A significant reduction in substrate coupling noise is also demonstrated.;In synchronous digital ICs, switching noise affects the timing characteristics of a circuit by generating additional delay uncertainty, possibly degrading system performance or causing a circuit to fail. Interdependent setup and hold times are characterized and exploited to compensate for delay uncertainty, producing a more robust circuit tolerant to switching noise. The proposed algorithms are demonstrated on industrial circuits, verifying the efficiency of exploiting interdependence in reducing delay uncertainty. The research presented in this dissertation provides methodologies and algorithms for designing both mixed-signal and synchronous digital ICs with superior noise performance and enhanced signal integrity.
机译：集成电路（IC）的设计和制造的不断进步，使同一时钟上的时钟频率远高于几GHz的芯片上集成了超过20亿个晶体管。这些改进引发了片上系统（SoC）和系统级封装（SiP）时代，从而极大地改变了对复杂IC噪声的传统理解。传统上，设备噪声一直是模拟IC的主要关注点，而数字IC通常被认为相对抗噪声。由于集成度更高和信号转换时间更快，这种情况已发生了显着变化。具体来说，开关噪声已成为混合信号和高性能同步数字IC的主要设计标准。电路的电源/接地节点上的电压波动（即电源/接地噪声）是一种影响两者的开关噪声混合信号和数字IC。提出了一种方法，该方法可精确估计带有去耦电容器的感应式电源/地分配网络中最坏情况下的电源/地噪声。在混合信号IC中，电源/接地噪声会通过单片基板影响高度敏感的模拟/ RF模块，从而降低关键性能参数，例如增益，带宽，动态范围，总谐波失真和相位噪声。提出了几种方法来有效地建模和减轻混合信号IC中的基板噪声耦合。建议的分析过程确定电路的噪声特性，从而确定适当的噪声隔离技术。还提出了一种通过合并噪声感知标准单元来降低噪声的方法。所提出的方法和算法已通过工业电路验证，在保持噪声电压足够准确的同时，在计算效率上也有显着提高。还证明了基板耦合噪声的显着降低。在同步数字IC中，开关噪声会产生额外的延迟不确定性，从而可能降低系统性能或导致电路故障，从而影响电路的时序特性。相互关联的建立时间和保持时间经过表征，可以用来补偿延迟不确定性，从而产生更强大的电路，能够承受开关噪声。所提出的算法在工业电路上得到了证明，验证了利用相互依赖性降低延迟不确定性的效率。本文的研究提供了设计具有优异噪声性能和增强信号完整性的混合信号和同步数字IC的方法和算法。

著录项

  • 作者

    Salman, Emre.;

  • 作者单位

    University of Rochester.;

  • 授予单位 University of Rochester.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 348 p.
  • 总页数 348
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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