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Computational Analysis of Impact Loading on Wafer Level Chip Scale Packages Mounted on Printed Circuit Boards of Varying Thickness.

机译：对安装在厚度不同的印刷电路板上的晶圆级芯片级封装的冲击载荷的计算分析。

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作者
Mahmood, Anik.;
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作者单位

The University of Texas at Arlington.;

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授予单位 The University of Texas at Arlington.;
学科 Mechanical engineering.;Packaging.
学位 M.S.M.E.
年度 2016
页码 104 p.
总页数 104
原文格式 PDF
正文语种 eng
中图分类
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专利

1. Gold Embrittlement of Solder Joints in Wafer-Level Chip-Scale Package on Printed Circuit Board With Ni/Au Surface Finish [J] . Huang X., Lee S. W. R., Li M., IEEE transactions on electronics packaging manufacturing . 2008,第3期

机译：镍/金表面处理的印刷电路板晶圆级芯片级封装中的焊点金脆
2. Elastic, elastic-plastic and creep analyses of Wafer level chip scale package solder joints on microvia build-up printed circuit boards [J] . John H. Lau Circuit World . 2000,第1期

机译：微孔积层印刷电路板上晶圆级芯片级封装焊点的弹性，弹塑性和蠕变分析
3. High-G drop impact response and failure analysis of a chip packaged printed circuit board [J] . S.T. Jenq, H.S. Sheu, Chang-Lin Yeh, International journal of impact engineering . 2007,第10期

机译：芯片封装印刷电路板的高G跌落冲击响应和故障分析
4. Creep Analysis of Wafer Level Chip Scale Package (WLCSP) with 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board [C] . John H. Lau, Stephen H. Pan, Chris Chang ASME international mechanical engineering congress and exposition . 2000

机译：具有96.5Sn-3.5Ag和100In无铅焊点和Microvia积层印刷电路板的晶圆级芯片级封装（WLCSP）的蠕变分析
5. Experimental and Simulation Board Level Reliability Assessment of Wafer Level Chip Scale Packages (WCSPs) Under Thermal Cycling [D] . Khan, Hassaan Ahmad 2015

机译：热循环下晶圆级芯片级封装（WCSP）的实验和仿真板级可靠性评估
6. Character Recognition of Components Mounted on Printed Circuit Board Using Deep Learning [O] . Sumyung Gang, Ndayishimiye Fabrice, Daewon Chung, 2021

机译：使用深度学习安装在印刷电路板上的部件的字符识别
7. Surface mounting of leadless chip carriers on various printed circuit board type substrates [O] . 1983

机译：各种印刷电路板型基板上无铅芯片载体的表面安装
8. Low Cycle Fatigue of Surface Mounted Chip Carrier/Printed Wiring Board Joints [R] . Solomon, H. D. 1987

机译：表面贴装芯片载体/印刷线路板接头的低周疲劳

Computational Analysis of Impact Loading on Wafer Level Chip Scale Packages Mounted on Printed Circuit Boards of Varying Thickness.

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