A sustainable Evolvable Hardware (EH) system is developed for SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) using outlier detection and group testing-based assessment principles. The fault diagnosis methods presented herein leverage throughput-driven, relative fitness assessment to maintain resource viability autonomously. Group testing-based techniques are developed for adaptive input-driven fault isolation in FPGAs, without the need for exhaustive testing or coding-based evaluation. The techniques maintain the device operational, and when possible generate validated outputs throughout the repair process.;Adaptive fault isolation methods based on discrepancy-enabled pair-wise comparisons are developed. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, a method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. The results from the analytical FPGA model are demonstrated via a self-healing, self-organizing evolvable hardware system. Reconfigurability of the SRAM-based FPGA is leveraged to identify logic resource faults which are successively excluded by group testing using alternate device configurations. This simplifies the system architect's role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance versus availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an Observer-Controller model. Results are demonstrated using a Data Encryption Standard (DES) core that occupies approximately 305 FPGA slices on a Xilinx Virtex-II Pro FPGA. With a single simulated stuck-at-fault, the system identifies a completely validated replacement configuration within three to five positive tests. The approach demonstrates a readily-implemented yet robust organic hardware application framework featuring a high degree of autonomous self-control.
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机译：使用异常检测和基于组测试的评估原理，为基于SRAM的可重配置现场可编程门阵列（FPGA）开发了可持续的可进化硬件（EH）系统。本文介绍的故障诊断方法利用吞吐量驱动的相对适应性评估来自动维护资源生存能力。基于组测试的技术被开发用于FPGA中自适应输入驱动的故障隔离，而无需进行详尽的测试或基于编码的评估。这些技术可以使设备保持运行状态，并在可能的情况下在整个维修过程中生成经过验证的输出。开发了基于差异启用的成对比较的自适应故障隔离方法。通过观察多个并发错误检测（CED）配置的差异特征，基于使用差异镜像逻辑的成对并行评估，开发了一种用于故障稳健检测的方法。通过自修复，自组织的可演化硬件系统演示了分析型FPGA模型的结果。利用基于SRAM的FPGA的可重新配置性来确定逻辑资源故障，这些故障可通过使用备用设备配置进行的组测试连续排除。通过使用高级硬件描述语言（HDL）和系统级性能与可用性操作点，可以简化系统架构师在功能定义中的角色。使用Observer-Controller模型监视和维护系统可用性，吞吐量和隔离故障的平均时间。使用数据加密标准（DES）内核证明了结果，该内核在Xilinx Virtex-II Pro FPGA上大约占据305个FPGA片。通过单个模拟的故障定位卡，系统可以在三到五个阳性测试中识别出经过完全验证的替换配置。该方法演示了一个易于实现但功能强大的有机硬件应用程序框架，该框架具有高度的自主控制能力。
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