With the development of CMP technology and the shrinking of flash memory critical dimensions,more requirements are imposed on poly surface performance and the overlay between different photo layers.CMP technology is also used for floating gate poly planarization.There will have big impacts on device electric parameters and the following processes if floating gate poly thickness uniformity and poly surface quality are not good.Therefore,how to get a stable,uniform and good surface quality poly gate is very important for mass production.In this dissertation,poly residue and dishing issue have been studied during developing 90nm embedded flash FG（Floating Gate）CMP process.Getting much improvement by the experiments to reduce STI（Shallow Trench Isolation）HDP（High Density Plasma）dishing and improve the poly thickness uniformity on different AA（Active Area）pattern.%随着CMP技术的日益发展和闪存特征尺寸的越来越小以及对多晶硅表面形态及前后层次间套准要求的提高,这一技术也被用于嵌入式闪存产品中浮动栅多晶硅的平坦化。浮动栅多晶硅厚度及表面形态对器件的电性参数及后续工艺影响较大,因此怎样得到一个稳定、厚度均匀及表面形态佳的浮动栅多晶硅显得至关重要。文章就以在90nm嵌入式闪存开发浮动栅CMP过程中出现的多晶硅残余及多晶硅凹陷问题进行原因分析,通过减少化学机械研磨过程中产生的碟形凹陷及提高单个芯片内不同有源区上的多晶硅厚度的均匀性进行实验和研究,使浮动栅研磨后的多晶硅残余和多晶硅凹陷得到明显的改善。
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