Correction to: AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

Manjith Baby Chellam; Natarajan Ramasubramanian

首页> 外文期刊>Arabian Journal for Science and Engineering >Correction to: AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

【24h】

Correction to: AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

机译：更正为：FPGA上的AES硬件加速器，具有改进的吞吐量和资源效率

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

页面导航

著录项
相似文献
相关主题

著录项

来源
《Arabian Journal for Science and Engineering》 |2019年第3期|2861-2861|共1页
作者
Manjith Baby Chellam; Natarajan Ramasubramanian;
展开▼
作者单位

Natl Inst Technol, Dept Comp Sci & Engn, Tiruchchirappalli, Tamil Nadu, India;

Natl Inst Technol, Dept Comp Sci & Engn, Tiruchchirappalli, Tamil Nadu, India;

展开▼
收录信息美国《科学引文索引》(SCI);
原文格式 PDF
正文语种 eng
中图分类
关键词

相似文献

外文文献
中文文献
专利

1. Correction to: AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency [J] . Manjith Baby Chellam, Natarajan Ramasubramanian Arabian Journal for Science and Engineering . 2019,第3期

机译：校正：AES硬件加速器在FPGA上提高吞吐量和资源效率
2. AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency [J] . Manjith Baby Chellam, Ramasubramanian Natarajan Arabian Journal for Science and Engineering . 2018,第12期

机译：FPGA上的AES硬件加速器，具有改进的吞吐量和资源效率
3. Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes [J] . Changqing Xu, Wenrui Zhang, Yu Liu, Frontiers in Neuroscience . 2020,第4期

机译：使用时间压缩支撑多穗码的硬件尖峰神经加速器的吞吐量和效率
4. DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs [C] . Jacob T. Grycel, Robert J. Walls IEEE International Symposium on Circuits and Systems . 2020

机译：DRAB-LOCUS：用于FPGA上的硬件加速器共置的高效区域性AES架构
5. Hardware-Software Techniques for Improving Resource Efficiency in Datacenters [D] . ?Kulkarni, Neeraj Sanjay 2020

机译：用于提高数据中心资源效率的硬件软件技术
6. Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes [O] . Changqing Xu, Wenrui Zhang, Yu Liu, 2020

机译：使用时间压缩支撑多穗码的硬件尖峰神经加速器的吞吐量和效率
7. High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis [O] . Morgan Ledwon, Bruce F. Cockburn, Jie Han 2020

机译：基于高吞吐量FPGA的硬件加速器，用于使用高级合成放气的压缩和减压

Correction to: AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

著录项

相似文献

相关主题

期刊订阅