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首页> 外文期刊>Journal of Ovonic Research >Design and analysis of normally-on 4H-sic vertical junction field effect transistor (VJFET) using sentaurus TCAD simulation
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Design and analysis of normally-on 4H-sic vertical junction field effect transistor (VJFET) using sentaurus TCAD simulation

机译：使用Sentaurus TCAD模拟设计和分析常导4H-sic垂直结场效应晶体管（VJFET）

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摘要

This paper is intended to simulate the performance of normally on 4H SiC vertical junction field effect transistor (VJFET) for high voltage applications. Sentaurus TCAD simulator was used to investigate the breakdown voltages with different channel width (0.5 to 0.9 μm) under the negative bate bias. It is observed that high negative voltage is needed most likely for normally on devices. Simulation results show that breakdown voltage decreases with increasing negative gate voltage. By combining the device geometrical parameters model fitting parameters and device physics, breakdown voltage, distribution of electric field and leakage current was observed. In addition, the effect of drift doping on the breakdown voltage is discussed in details. Moreover, drift doping dependent breakdown voltage was measured with the influence of channel width and drift layer thickness. It was observed that breakdown voltage decrease with increasing drift doping. Also for a given channel width, high breakdown voltage was found in case of high drift layer thickness. The maximum breakdown voltage approximately 11 kV was examined with drain leakage current of the order of 10 7 A. The novelty of the proposed design has strong correlation with already published experimental data.
机译：本文旨在模拟通常用于高压应用的4H SiC垂直结场效应晶体管（VJFET）的性能。使用Sentaurus TCAD仿真器研究在负bate偏压下具有不同通道宽度（0.5至0.9μm）的击穿电压。可以看出，通常在设备上很可能需要高负电压。仿真结果表明，击穿电压随着负栅极电压的增加而减小。通过结合器件几何参数模型拟合参数和器件物理特性，观察击穿电压，电场分布和泄漏电流。另外，详细讨论了漂移掺杂对击穿电压的影响。此外，在沟道宽度和漂移层厚度的影响下，测量了取决于漂移掺杂的击穿电压。观察到击穿电压随着漂移掺杂的增加而降低。同样对于给定的沟道宽度，在高漂移层厚度的情况下发现高击穿电压。在大约10 7 A的漏极泄漏电流下检查了大约11 kV的最大击穿电压。所提出设计的新颖性与已经发表的实验数据具有很强的相关性。

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