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首页> 外文期刊>IOSR Journal of Electronics and Communication Engineering >FPGA Based Implementation of AES Encryption and Decryption with Low Power Multiplexer LUT Based S-Box
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FPGA Based Implementation of AES Encryption and Decryption with Low Power Multiplexer LUT Based S-Box

机译：基于FPGA的低功耗多路复用器LUT基于S-Box的AES加密和解密实现

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摘要

Encryption is important to keep the confidentiality of data. There are many of encryption algorithms to ensure the data, but should be the select the algorithm depended on the fast, strong and implementation. For that choose the advance encryption standard (AES) algorithm for encryption data because speed and easy implementation on small devices and some the feature for it. In this paper, implementation of encryption and decryption of AES algorithm is presented with a High Secured Low Power Multiplexer Look-Up-Table (MLUT) based Substitution-Box (S-Box) . The main feature in the proposed MLUT based S-Box is that, it is implemented based on 256-byte to 1-byte multiplexer with a 256-byte memory instead of the conventional implementation of employing multiplication inversion in GF(2~8) and aifine transformation. Thus, the proposed S-Box is simpler in circuit implementation and lower in power dissipation.%AES;Multiplexer LUT;S-Box;FPGA
机译：加密对于保持数据的机密性很重要。保证数据安全的加密算法很多，但选择算法要取决于其快速，强大和实现。为此，请选择用于加密数据的高级加密标准（AES）算法，因为在小型设备上的速度和简便实现及其某些功能。本文提出了一种基于高安全性的低功耗多路复用器查找表（MLUT）的替代盒（S-Box）来实现AES算法的加密和解密。所提出的基于MLUT的S-Box的主要特点是，它是基于具有256字节内存的256字节至1字节多路复用器实现的，而不是在GF（2〜8）和aifine转换。因此，所提出的S-Box在电路实现方面更简单并且功耗更低。％AES; Multiplexer LUT; S-Box; FPGA

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