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首页> 外文期刊>Japanese Journal of Applied Physics. Part 1, Regular Papers, Brief Communications & Review Papers >New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration
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New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

机译：利用芯片对晶圆键合实现最终超级芯片集成的新型三维集成技术

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摘要

A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In-Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm~2 and ranging in thickness from 30 to 90 μm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.
机译：使用芯片对晶圆键合技术的新的三维（3D）集成技术提供了最终的超级芯片集成，其中可以将不同尺寸的各种芯片垂直堆叠并通过许多垂直互连进行电连接。我们研究了垂直互连形成，芯片对准，芯片到晶圆键合，粘合剂注入和芯片薄化的几种关键技术，以将已知的良好管芯（KGD）垂直堆叠到3D LSI芯片中。通过使用这些关键技术，展示了具有垂直互连的3D LSI测试芯片的成功制造，该垂直互连包括In-Au微凸块和填充有多晶硅（poly-Si）的掩埋互连。测试芯片由5、6和7 mm〜2三种非常薄的芯片组成，厚度范围为30至90μm。每个芯片都使用低粘度环氧树脂粘合剂作为电介质材料紧密结合。

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